Contents
Main
CY14B102L, CY14B102N
2 Mbit (256K x 8/128K x 16) nvSRAM
Features
20 ns, 25 ns, and 45 ns Access Times Internally organized as 256K x 8 (CY14B102L) or 128K x 16
(CY14B102N)
Hands off Automatic STORE on power down with only a small
CY14B102L, CY14B102N
Document #: 001-45754 Rev. *B Page 2 of 24
Pinouts
(x8)
Top View
Pin Definitions
(x16)
Pinouts
CY14B102L, CY14B102N
Device Operation
SRAM Read
SRAM Write
AutoStore Operation
Hardware RECALL (Power Up)
Software STORE
Software RECALL
Preventing AutoStore
Data Protection
Noise Considerations
Maximum Ratings
Operating Range
DC Electrical Characteristics
AC Test Conditions
Data Retention and Endurance
Capacitance
Thermal Resistance
AC Switching Characteristics
Switching Waveforms
CY14B102L, CY14B102N
Figure 7. SRAM Read Cycle #2: CE and OE Controlled[3, 15, 19]
Figure 8. SRAM Write Cycle #1: WE Controlled[3, 18, 19, 20]
Figure 9. SRAM Write Cycle #2: CE Controlled[3, 18, 19, 20]
Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled[3, 18, 19, 20]
AutoStore/Power Up RECALL
Figure 11. AutoStore or Power Up RECALL
Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE/RECALL cycle parameters are listed.[26, 27]
Figure 12. CE and OE Controlled Software STORE/RECALL Cycle[27]
Figure 13. Autostore Enable/Disable Cycle
CY14B102L, CY14B102N
Hardware STORE Cycle
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Figure 14. Hardware STORE Cycle[22]
Figure 15. Soft Sequence Processing
Truth Table For SRAM Operations
For x8 Configuration
For x16 Configuration
Page
Page
Ordering Information
Part Numbering Nomenclature
I - Industrial (40 to 85C)
Package Diagrams
Figure 16. 44-Pin TSOP II (51-85087)
TOPVIEW BOTTOMVIEW
51-85087-*A
Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)
Package Diagrams
51-85128-*D
Page
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