Cypress STK11C68-5 AC Switching Characteristics , Switching Waveforms

STK11C68-5 (SMD5962-92324)
Document Number: 001-51001 Rev. *A Page 7 of 15
Figure 7. SRAM Read Cycle 2: CE and OE Controlled [4]
AC Switching Characteristics
SRAM Read Cycle
Parameter Description 35 ns 45 ns 55 ns Unit
Min Max Min Max Min Max
Cypress
Parameter Alt
tACE tELQV Chip Enable Access Time 35 45 55 ns
tRC [4] tAVAV,
tELEH
Read Cycle Time 35 45 55 ns
tAA [5] tAVQV Address Access Time 35 45 55 ns
tDOE tGLQV Output Enable to Data Valid 15 20 35 ns
tOHA [5] tAXQX Output Hold After Address Change 5 5 5 ns
tLZCE [6] tELQX Chip Enable to Output Active 5 5 5 ns
tHZCE [6] tEHQZ Chip Disable to Output Inactive 13 15 25 ns
tLZOE [6] tGLQX Output Enable to Output Active 0 0 0 ns
tHZOE [6] tGHQZ Output Disable to Output Inactive 13 15 25 ns
tPU [3] tELICCH Chip Enable to Power Active 0 0 0 ns
tPD [3] tEHICCL Chip Disable to Power Standby 35 45 55 ns
Switching Waveforms Figure 6. SRAM Read Cycle 1: Address Controlled [4, 5]
Notes
4. WE must be High during SRAM Read cycles.
5. I/O state assumes CE and OE < VIL and WE > VIH; device is continuously selected.
6. Measured ± 200 mV from steady state output voltage.
W
5&
W
$$
W
2+$
$''5(66
'4'$7$287 '$7$9$/,'
$''5(66
W
5&
&(
W
$&(
W
/=&(
W
3'
W
+=&(
2(
W
'2(
W
/=2(
W
+=2(
'$7$9$/,'
$&7,9(
67$1'%<
W
38
'4'$7$287
,&&
[+] Feedback