Cypress STK11C68-5 manual Low Average Active Power, Best Practices, Hardware Mode Selection A12-A0

STK11C68-5 (SMD5962-92324)

Low Average Active Power Figure 4. Current Versus Cycle Time (Write)

CMOS technology provides the STK11C68-5 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 3 and Figure 4 shows the relationship between ICC and Read or Write cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK11C68-5 depends on the following items:

■Duty cycle of chip enable

■Overall cycle rate for accesses

■Ratio of Reads to Writes

■CMOS versus TTL input levels

■Operating temperature

■VCC level

■I/O loading

Figure 3. Current Versus Cycle Time (Read)

Best Practices

Cypress nvSRAM products have been used effectively for over 15 years. While ease of use is one of the product’s main system values, the experience gained from working with hundreds of applications has resulted in the following suggestions as best practices:

■The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer’s sites sometimes reprograms these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. The end product’s firmware must not assume that an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration.

■Cold or warm boot status, and so on must always program a unique NV pattern (for example, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test. This is to ensure these system routines work consistently.

Table 1. Hardware Mode Selection

CE	WE	A12–A0	Mode	I/O	Notes
L	H	0x0000	Read SRAM	Output Data	[1]
		0x1555	Read SRAM	Output Data
		0x0AAA	Read SRAM	Output Data
		0x1FFF	Read SRAM	Output Data
		0x10F0	Read SRAM	Output Data
		0x0F0F	Nonvolatile STORE	Output High Z
L	H	0x0000	Read SRAM	Output Data	[1]
		0x1555	Read SRAM	Output Data
		0x0AAA	Read SRAM	Output Data
		0x1FFF	Read SRAM	Output Data
		0x10F0	Read SRAM	Output Data
		0x0F0E	Nonvolatile RECALL	Output High Z

Note

1. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.

Document Number: 001-51001 Rev. *A Page 4 of 15

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