STK11C68-5 (SMD5962-92324)

Software Controlled STORE/RECALL Cycle

The software controlled STORE/RECALL cycle follows. [10, 11]

 

Parameter

Alt

Description

35 ns

 

45 ns

55 ns

Unit

 

Min

Max

Min

 

Max

Min

Max

 

 

 

 

 

 

 

tRC

tAVAV

STORE/RECALL Initiation Cycle Time

35

 

45

 

 

55

 

ns

t

SA

[10]

tAVEL

Address Setup Time

0

 

0

 

 

0

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

t

 

[10]

tELEH

Clock Pulse Width

25

 

30

 

 

35

 

ns

 

CW

 

 

 

 

 

 

 

 

 

 

t

 

[10]

tELAX

Address Hold Time

20

 

20

 

 

20

 

ns

 

HACE

 

 

 

 

 

 

 

 

 

 

tRECALL[10]

 

RECALL Duration

 

20

 

 

20

 

20

μs

Switching Waveform

Figure 11. CE Controlled Software STORE/RECALL Cycle [10]

ADDRESS

CE

OE

DQ (DATA)

tRC

ADDRESS # 1

tSA

 

 

 

tSCE

 

 

tHACE

DATA VALID

tRC

ADDRESS # 6

tSTORE / tRECALL

HIGH IMPEDANCE

DATA VALID

Notes

10.The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).

11.The six consecutive addresses must be read in the order listed in Table 1 on page 4. WE must be HIGH during all six consecutive cycles.

Document Number: 001-51001 Rev. *A

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Cypress STK11C68-5 manual Software Controlled STORE/RECALL Cycle, Switching Waveform, Min Max