Cypress STK11C68-5 STK11C68-5 (SMD5962-92324)

STK11C68-5 (SMD5962-92324)
Document Number: 001-51001 Rev. *A Page 3 of 15
Device Operation
The STK11C68-5 is a versatile memory chip that provides
several modes of operation. The STK11C68-5 can operate as a
standard 8K x 8 SRAM. It has an 8K x 8 Nonvolatile Elements
shadow to which the SRAM information can be copied or from
which the SRAM can be updated in nonvolatile mode.
SRAM Read
The STK11C68-5 performs a Read cycle whenever CE and OE
are LOW while WE is HIGH. The address specified on pins A0–12
determines the 8,192 data bytes accessed. When the Read is
initiated by an address transition, the outputs are valid after a
delay of tAA (Read cycle 1). If the Read is initiated by CE or OE,
the outputs are valid at tACE or at tDOE, whichever is later (Read
cycle 2). The data outputs repeatedly respond to address
changes within the tAA access time without the need for
transitions on any control input pins. They remain valid until
another address change or until CE or OE is brought HIGH, or
WE is brought LOW.
SRAM Write
A Write cycle is performed whenever CE and WE are LOW. The
address inputs must be stable before entering the Write cycle
and must remain stable until either CE or WE goes HIGH at the
end of the cycle. The data on the common I/O pins DQ0–7 are
written into the memory if it has valid tSD. This is done before the
end of a WE controlled Write or before the end of an CE
controlled Write. Keep OE HIGH during the entire Write cycle to
avoid data bus contention on common I/O lines. If OE is left LOW,
internal circuitry turns off the output buffers tHZWE after WE goes
LOW.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The STK11C68-5 software
STORE cycle is initiated by executing sequential CE controlled
Read cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of Reads from specific addresses is used
for STORE initiation, it is important that no other Read or Write
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following Read
sequence is performed:
1.Re ad address 0x0000, Valid READ
2.Re ad address 0x1555, Valid READ
3.Read address 0x0AAA, Valid READ
4.Re ad address 0x1FFF, Valid READ
5.Re ad address 0x10F0, Valid READ
6.Read address 0x0F0F, Initiate STORE cycle
The software sequence is clocked with CE controlled Reads.
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
Read cycles and not Write cycles are used in the sequence. It is
not necessary that OE is LOW for a valid sequence. After the
tSTORE cycle time is fulfilled, the SRAM is again activated for
Read and Write operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of Read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled Read operations is
performed:
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0E, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for Read and Write operations. The RECALL operation
does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC <
VRESET), an internal RECALL request is latched. When VCC
once again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
If the STK11C68-5 is in a Write state at the end of power up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
and system VCC or between CE and system VCC.
Hardware Protect
The STK11C68-5 offers hardware protection against inadvertent
STORE operation and SRAM Writes during low voltage
conditions. When VCAP < VSWITCH, all externally initiated STORE
operations and SRAM Writes are inhibited.
Noise Considerations
The STK11C68-5 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and VSS, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
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