64 Kbit (8K x 8) SoftStore nvSRAM
Features
■35 ns, 45 ns, and 55 ns access times
■Pin compatible with industry standard SRAMs
■Software initiated nonvolatile STORE
■Unlimited Read and Write endurance
■Automatic RECALL to SRAM on power up
■Unlimited RECALL cycles
■1,000,000 STORE cycles
■100 year data retention
■Single 5V ± 10% operation
■Military temperature
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Functional Description
The Cypress
Logic Block Diagram
A5
A6
Quantum Trap
128 X 512
STORE
VCC VCAP
POWER |
CONTROL |
A7
A8
A9
A11 A12
ROW DECODER
STATIC RAM
ARRAY
128 X 512
RECALL
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| RECALL |
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| CONTROL |
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| SOFTWARE |
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| A0 - A12 | |||
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| DETECT |
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DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
COLUMN I/O
BUFFERS |
| COLUMN DEC |
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INPUT | A | 0 A1 A2 A3 A4 A10 |
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OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court | • | San Jose, CA | • | |
Document Number: |
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| Revised April 07, 2009 |
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