Cypress STK12C68-5 STK12C68-5 (SMD5962-94599)

STK12C68-5 (SMD5962-94599)
Document Number: 001-51026 Rev. ** Page 12 of 18
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [18]
Parameter Alt Description 35 ns 55 ns Unit
Min Max Min Max
tRC[14] tAVAV STORE/RECALL Initiation Cycle Time 35 55 ns
tSA[17] tAVEL Address Setup Time 0 0 ns
tCW[17] tELEH Clock Pulse Width 25 30 ns
tHACE[17] tELAX Address Hold Time 20 20 ns
tRECALL RECALL Duration 20 20 μs
Switching Waveform Figure 13. CE Controlled Software STORE/RECALL Cycle [18]
t
RC
t
RC
t
SA
t
SCE
t
HACE
t
STORE
/ t
RECALL
DATAVALID
DATAVALID
6#SSERDDA1#SSERDDA
HIGH IMPEDANCE
ADDRESS
CE
OE
DQ (DATA)
Notes
17.The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).
18.The six consecutive addresses must be read in the order listed in Table 1 on page 6. WE must be HIGH during all six consecutive cycles.
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