AC Switching Characteristics
SRAM Read Cycle
Parameter | Description |
| 35 ns |
| 55 ns | Unit | |||
Cypress | Alt | Min |
| Max | Min |
| Max | ||
Parameter |
|
|
|
| |||||
|
|
|
|
|
|
|
|
| |
tACE | tELQV | Chip Enable Access Time |
|
| 35 |
|
| 55 | ns |
tRC [7] | tAVAV, tELEH | Read Cycle Time | 35 |
|
| 55 |
|
| ns |
tAA [8] | tAVQV | Address Access Time |
|
| 35 |
|
| 55 | ns |
tDOE | tGLQV | Output Enable to Data Valid |
|
| 15 |
|
| 35 | ns |
tOHA [8] | tAXQX | Output Hold After Address Change | 5 |
|
| 5 |
|
| ns |
tLZCE [9] | tELQX | Chip Enable to Output Active | 5 |
|
| 5 |
|
| ns |
tHZCE [9] | tEHQZ | Chip Disable to Output Inactive |
|
| 10 |
|
| 12 | ns |
tLZOE [9] | tGLQX | Output Enable to Output Active | 0 |
|
| 0 |
|
| ns |
tHZOE [9] | tGHQZ | Output Disable to Output Inactive |
|
| 10 |
|
| 12 | ns |
tPU [6] | tELICCH | Chip Enable to Power Active | 0 |
|
| 0 |
|
| ns |
tPD [6] | tEHICCL | Chip Disable to Power Standby |
|
| 35 |
|
| 55 | ns |
Switching Waveforms
Figure 8. SRAM Read Cycle 1: Address Controlled [7, 8]
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W5&
W$$
W2+$
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Figure 9. SRAM Read Cycle 2: CE and OE Controlled [7]
$''5(66
&(
2(
'4 '$7$287
,&&
W5&
W$&(
W/=&(
W'2(
W/=2(
W38 
$&7,9(
67$1'%<
W3'
W+=&(
W+=2(
'$7$9$/,'
Notes
7.WE and HSB must be High during SRAM Read cycles.
8.Device is continuously selected with CE and OE both Low.
9.Measured ±200 mV from steady state output voltage.
Document Number: | Page 9 of 18 |
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