STK12C68-5 (SMD5962-94599)
Document Number: 001-51026 Rev. ** Page 9 of 18
AC Switching Characteristics
SRAM Read Cycle
Parameter Description 35 ns 55 ns Unit
Min Max Min Max
Cypress
Parameter Alt
tACE tELQV Chip Enable Access Time 35 55 ns
tRC [7] tAVAV, tELEH Read Cycle Time 35 55 ns
tAA [8] tAVQV Address Access Time 35 55 ns
tDOE tGLQV Output Enable to Data Valid 15 35 ns
tOHA [8] tAXQX Output Hold After Address Change 5 5 ns
tLZCE [9] tELQX Chip Enable to Output Active 5 5 ns
tHZCE [9] tEHQZ Chip Disable to Output Inactive 10 12 ns
tLZOE [9] tGLQX Output Enable to Output Active 0 0 ns
tHZOE [9] tGHQZ Output Disable to Output Inactive 10 12 ns
tPU [6] tELICCH Chip Enable to Power Active 0 0 ns
tPD [6] tEHICCL Chip Disable to Power Standby 35 55 ns
Switching Waveforms Figure 8. SRAM Read Cycle 1: Address Controlled [7, 8]
Figure 9. SRAM Read Cycle 2: CE and OE Controlled [7]
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Notes
7. WE and HSB must be High during SRAM Read cycles.
8. Device is continuously selected with CE and OE both Low.
9. Measured ±200 mV from steady state output voltage.
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