Figure 4. AutoStore Inhibit Mode
Hardware STORE (HSB) Operation
The
SRAM READ and WRITE operations, that are in progress when HSB is driven LOW by any means, are given time to complete before the STORE operation is initiated. After HSB goes LOW, the
During any STORE operation, regardless of how it is initiated, the
If HSB is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC < VRESET), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete.
If the
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The
Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If they intervene, the sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ sequence is performed:
1.Read address 0x0E38, Valid READ
2.Read address 0x31C7, Valid READ
3.Read address 0x03E0, Valid READ
4.Read address 0x3C1F, Valid READ
5.Read address 0x303F, Valid READ
6.Read address 0x0FC0, Initiate STORE cycle
The software sequence is clocked with CE controlled READs. When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that READ cycles and not WRITE cycles are used in the sequence. It is not necessary that OE is LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is again activated for READ and WRITE operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations is performed:
1.Read address 0x0E38, Valid READ
2.Read address 0x31C7, Valid READ
3.Read address 0x03E0, Valid READ
4.Read address 0x3C1F, Valid READ
5.Read address 0x303F, Valid READ
6.Read address 0x0C63, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data is cleared, and then the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is once again ready for READ and WRITE operations. The RECALL operation does not alter the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times.
Document Number: | Page 4 of 17 |
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