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AC Switching Characteristics |
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SRAM Read Cycle |
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| Parameter |
| Description | 35 ns |
| 45 ns | Unit | ||||
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| Cypress | Alt |
| Min |
| Max | Min |
| Max | |||
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tACE |
| tELQV |
| Chip Enable Access Time |
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| 35 |
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| 45 | ns | ||
t | RC | [9] |
| tAVAV, tELEH |
| Read Cycle Time | 35 |
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| 45 |
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| ns |
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t | AA | [10] | tAVQV |
| Address Access Time |
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| 35 |
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| 45 | ns | |
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tDOE |
| tGLQV |
| Output Enable to Data Valid |
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| 15 |
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| 20 | ns | ||
t |
| [10] | tAXQX |
| Output Hold After Address Change | 5 |
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| 5 |
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| OHA |
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t | LZCE | [11] | tELQX |
| Chip Enable to Output Active | 5 |
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t | HZCE | [11] | tEHQZ |
| Chip Disable to Output Inactive |
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| 15 | ns | |
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t | LZOE | [11] | tGLQX |
| Output Enable to Output Active | 0 |
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t | HZOE | [11] | tGHQZ |
| Output Disable to Output Inactive |
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| 15 | ns | |
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t | PU | [8] |
| tELICCH |
| Chip Enable to Power Active | 0 |
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t | PD | [8] |
| tEHICCL |
| Chip Disable to Power Standby |
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| 35 |
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| 45 | ns |
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Switching Waveforms | Figure 8. SRAM Read Cycle 1: Address Controlled [9, 10] |
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$''5(66
W5&
W$$
W2+$
'4 '$7$287 
'$7$9$/,'
Figure 9. SRAM Read Cycle 2: CE and OE Controlled [9]
$''5(66
&(
2(
'4 '$7$287
,&&
W5&
W$&(
W/=&(
W'2(
W/=2(
W38 
$&7,9(
67$1'%<
W3'
W+=&(
W+=2(
'$7$9$/,'
Notes
9.WE and HSB must be HIGH during SRAM Read cycles.
10.Device is continuously selected with CE and OE both Low.
11.Measured ±200 mV from steady state output voltage.
Document Number: | Page 9 of 17 |
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