Emerson PME1, PMT1 user manual TDM Interface Front Panel I/O, Field Width Function

TDM Interface: Front Panel I/O

Table 6-7:MDI Bit Field Format

Field:	Width:	Function1:
Start	2	The “01” transition frames the beginning of an MDI cycle.
		The MDI Interface is reset when the MDIO line (which is pulled up) is
		high for greater than 40 clocks.
OpCode	3	0002 Reserved
		0012 Reserved
		0102 Module ID Register Read (returns 0216)
		0112 Module Interrupt Register Read1
		Bits 0—3undefined
		Bit 4INT1—, from DS2153/DS2151 Channel 1
		Bit 5INT2—, from DS2153/DS2151 Channel 1
		Bit 6INT1—, from DS2153/DS2151 Channel 0
		Bit 7INT2—, from DS2153/DS2151 Channel 0
		1002 DS2153/DS2151 Channel 0 (TDMA) Register Write
		1012 DS2153/DS2151 Channel 1 (TDMB) Register Write
		1102 DS2153/DS2151 Channel 0 (TDMA) Register Read
		1112 DS2153/DS2151 Channel 1 (TDMB) Register Read
Address	8	Address of a T1 or E1 controller register (determined by 2153 or 2151
		interface controller) For ID register and interrupt register cycles the
		address field is ignored.
Data	8	Register Read/Write Data On read cycles the MDI protocol requires
		that the accessing application continue to clock the interface while
		waiting for the MDIO line to be driven low. Once low the following 8
		bits will be valid data.

1.These are read-only bits. You must enable, disable, or clear interrupts at the DS2153/DS2151 framer chip itself. The SR1 status register on each framer chip corresponds to bits 5 and 7. Similarly, the SR2 status register on each framer chip corresponds to bits 4 and 6.

FRONT PANEL I/O

Connectors P1 and P2 provide the TDM signals for the PmT1 and PmE1 front panel I/O con- figurations. The manufacturer part number for this eight-pin connector is Stewart Connec- tor Systems SS-610808-NF-P-5.

Figure 6-3:Front Panel I/O Connectors, P1 and P2

P2	P1
(TDMA - Channel 0)	(TDMB - Channel 1)

Pin 1

6-8

PmT1 and PmE1 User’s Manual 10002367-02