CPM Interrupt Handling, Dual-Port RAM | Emerson PMT1, PME1 specification

Serial I/O: The Communications Processor Module


	Priority:											Function:										Description:
	Priority:											Function:										Description:
											4											SCC1 Reception

											5											SCC1 Transmission

											6											SCC2 Reception

											7											SCC2 Transmission

											8											SCC3 Reception

											9											SCC3 Transmission

											10											SCC4 Reception

											11											SCC4 Transmission

											12											SMC1 Reception

											13											SMC1 Transmission

											14											SMC2 Reception

											15											SMC2 Transmission

											16											reserved
											17											reserved
											18											reserved
	Lowest										19											RISC Timers

CPM Interrupt Handling

The CPM RISC controller generates interrupts through the interrupt controller to the CPU. The interrupt vector is provided by the CPU.

The interrupt controller is the focal point for all internal and external interrupt requests by the CPM. It handles up to 28 interrupt sources (12 external, 16 internal) which may be assigned to a programmable interrupt level (1, 3, 5, 7). The priority in which interrupt sources are serviced is generally fixed (see the MPC860 PowerQUICC™ User’s Manual), but some flexibility is provided to modify the priority structure, particularly with respect to the SCCs.

Dual-Port RAM

The CPM has 8KB of SRAM configured as dual-port memory. It can be accessed by the RISC processor, the CPU, IDMAs, and SDMAs. The dual-port RAM has the following uses–any two of which can occur simultaneously:

•Store parameters associated with the SCCs and IDMAs

•Store buffer descriptors (describe the location of data buffers)

•Store data from the serial channels

•Store RAM microcode for the RISC processor

•Scratchpad RAM space for the user program

10002367-02

PmT1 and PmE1 User’s Manual

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Emerson PMT1, PME1 user manual CPM Interrupt Handling, Dual-Port RAM

PMT1, PME1 specifications

The Emerson PME1 and PMT1 are advanced solutions in the realm of process management and automation, designed to enhance the efficiency and effectiveness of industrial operations. These devices play a crucial role in improving process control and providing comprehensive data analysis, which can lead to increased productivity and reduced operational costs.

The PME1 is characterized by its robust design and highly flexible architecture, allowing it to adapt to a variety of industrial environments. It integrates seamlessly with existing systems and offers advanced connectivity options to ensure that data flow is uninterrupted across different platforms. This feature is particularly important in modern industrial settings where data silos can inhibit operational efficiency.

The PMT1, on the other hand, focuses on real-time monitoring and telemetry. Its streamlined interface allows for quick access to key metrics, enabling operators to make informed decisions promptly. This is crucial in processes where timing is essential and minor delays can lead to significant financial losses. The PMT1 supports both wired and wireless communication protocols, ensuring that data is transmitted reliably irrespective of operational conditions.

One of the main features of both the PME1 and PMT1 is their integration of cutting-edge predictive analytics. With machine learning capabilities, these devices can analyze patterns and trends within the data, providing insights that can preemptively address potential issues before they escalate into significant problems. This predictive capability contributes to minimizing downtime and optimizing maintenance schedules, thus enhancing the overall lifecycle of equipment.

Another significant characteristic of the PME1 and PMT1 is their user-friendly interface. The intuitive design allows operators of all skill levels to navigate the systems with ease, minimizing training time and increasing overall productivity. With customizable dashboards, users can tailor their views to highlight the most relevant data for their specific operational needs.

In terms of security, both devices utilize advanced cybersecurity measures to protect sensitive data from unauthorized access. This is becoming increasingly important as industries rely more on digital solutions, and the potential risks associated with data breaches grow.

In summary, the Emerson PME1 and PMT1 are sophisticated tools designed for modern industrial applications, combining powerful features, advanced technologies, and essential characteristics. Their ability to provide real-time data analysis, ensure connectivity, and enhance predictive maintenance makes them invaluable for optimizing process management in various sectors. With a focus on user experience and data security, these devices are set to redefine efficiency and productivity in industrial operations.

Contents

PmT1 and PmE1 High Speed T1 and E1 Interface Module December Revision Level Principal Changes Date EMC Compliance Regulatory Agency Warnings & NoticesFCC Rules and Regulations Part FIC Facility Interface Industry Canada Rules and Regulations CS03 Model Name/Number Manufacturer’s NameProduct Contents Monitor Vii Viii Figures Blank Tables Xii Registers Blank Functional Overview Components and FeaturesOverview Physical Memory MAP Overview Physical Memory Map Hex Address Product Certification Physical Address Access See Hex Mode DescriptionOverview Additional Information Additional Information EMC Type Specification Device / Interface Document RoHS ComplianceTerminology and Notation Technical References Document Device / Interface PCI Local Bus Specification Overview Additional Information Width Depth Height SetupElectrostatic Discharge PMT1 and PME1 Circuit Board RN1 U32 Setup PmT1 and PmE1 Circuit Board Installation Setup InstallationConnectors Power Requirements Setup PmT1 and PmE1 SetupPMT1 and PME1 Setup Environmental Considerations Setup Reset MethodsReset Methods Troubleshooting Technical Support Setup Troubleshooting 5Serial Number and Product ID on Bottom Side Product Repair MPC860P Initialization Feature DescriptionCentral Processing Unit Decimal Required Address Register Hex Format Central Processing Unit MPC860P Initialization Vector Address Exception Hex Offset Central Processing Unit MPC860P Exception HandlingMPC860P Exception Handling Exception Hex Offset Central Processing Unit System Interface Unit SIUCPU Interrupts System Interface Unit SIU Timebase Counter Central Processing Unit Software ResetSoftware Reset MPC860 Parallel Port Configuration Optional BDM Header MPC860 Pin MPC860 Signal UseCentral Processing Unit Optional BDM Header Vflso Pin Signal Number Name Description Central Processing Unit Optional BDM Header I2C Eeprom Hex Address Register Name Bit Access DescriptionSocketed Flash ON-CARD Dram On-Card Memory Configuration On-card DramI2C Eeprom Operation Emerson Memory Map Cycle Total Clocks Wait States On-card Memory Sizing and TypeDram Timing Burst Write 1-11 Accesses Acronym Register Block Name Serial I/OCommunications Processor Module Priority Function Description Serial I/O The Communications Processor ModuleCPM Register Initialization Format Risc Controller Dual-Port RAM CPM Interrupt Handling Serial DMA Sdma Channels General Purpose TimersSerial I/O MPC860P Serial Interface Independent DMA Idma Channels Time Slot Assigner TSA Serial Communication Controllers SCCSerial Management Controllers SMC Uart Baud Rate Selection Serial I/O Uart Baud Rate Selection P14 Pin P0 Pin P2 Pin Signal Serial I/O Serial Connector Pin AssignmentsSerial Connector PIN Assignments RS422 RXCLK+ TDM Interface Quicc Pins to Transceiver Direction DS215xQ Function P2 Pin Signal Name P1 Pin Signal Name 1TDM and FDL Connectivity Diagram T1 or E1 Line Interface TDM Interface The T1 or E1 Line Interface T1 FDL Interface TDM Interface Configuring the T1 or E1 InterfaceConfiguring the T1 or E1 Interface FDL for Port P2 FDL for Port P1 Pin / Function TDM Interface The T1 FDL Interface Pin Description Port TDM Interface The Management Data Interface MDIManagement Data Interface MDI Field Width Function TDM Interface Front Panel I/OFront Panel I/O P1 and P2 Compu-Shield RJ-45 Jack Pin signal TDM Interface Front Panel I/O Size PCI Configuration RegistersPMC/PCI Interface PCI9060ES Register MAP PMC/PCI Interface PCI9060ES Register Map Local Configuration Registers PCI9060ES Initialization PMC/PCI Interface PCI9060ES InitializationShared Runtime Registers 4PCI9060ES PCI Configuration Register Initialization 5PCI9060ES Local Configuration Register Initialization Assigning Priorities Deadlocked CyclesRetries on Local Direct Master Cycles Retries on Direct Slave Cycles Avoiding the PCI9060ES Phantom Read Controlling Access LatencyHex Address Bits Register Field Factory Default Value hex PCI Interrupts PMC Connector PIN AssignmentsPMC/PCI Interface PCI Interrupts Pin P11 Signal P12 Signal PMC/PCI Interface PMC Connector Pin Assignments Pin P11 Signal PCI Bus Control Signals PMC/PCI Interface PMC Connector Pin Assignments PMC/PCI Interface PMC Connector Pin Assignments Monitor POWER-UP/RESET Sequence Factory Fields Purpose Default Optional Values Monitor Power-up/Reset Sequence Factory Fields Purpose Default Optional Values START-UP Display Monitor Start-upDisplay COMMAND-LINE Editor Monitor Command-line HistoryCOMMAND-LINE History Initializing Memory Command SyntaxMonitor Initializing Memory Typographic Conventions Boot CommandsBootbus Booteprom Monitor Boot Commands Device Type Download Format BootromBootserial MEMORY/REGISTER Commands Monitor Help CommandsHelp Commands Monitor Memory/Register Commands Writemem SetmemSwapmem Testmem Nvdisplay Monitor Nvram CommandsNvram Commands Writestr Nvset NvinitNvopen Configuring the Default Boot Device Nvupdate Monitor Nvram Commands Test Value Read on Failure Monitor Power-up Diagnostic/Test CommandsPOWER-UP DIAGNOSTIC/TEST Commands Power-up Test Sequence Bit Fail Mask Bit Eepromtest Monitor Remote Host CommandsRemote Host Commands Cachetest Binary Download Format CallDownload Transmode Configuring the Download Port Extended Address Record Hex-Intel Format End-of-file Record Data Record Here is a line-by-line explanation of the example file S0-records User Defined Motorola S-record Format S5-records Data Count Records S1-S2-and S3-records Data Records 05, 04 S7-S8-and S9-records Termination and Start Address Records Utilities Arithmetic CommandsMonitor Utilities Rand Monitor Errors and Screen MessagesErrors and Screen Messages Mul Monitor Function Reference Monitor Monitor Function Reference EEPROMAcc Monitor PmT1 and PmE1-Specific FunctionsPMT1 and PME1-SPECIFIC Functions ChangeBaud Misc InitBoard NvRamAcc NvHkOffset Cache Monitor MPC860P-Specific FunctionsSetUnExpIntFunct MPC860P-SPECIFIC Functions Handlerstruct Vector Cause of Exception HANDLERSTRUCT, which is the existing handler information Interrupts Atoh Monitor Standard Monitor FunctionsStatus Standard Monitor Functions BootUp IsLegal InitFifo Type Value Legal Characters MemMng See also MemTop, MemBase NVSupport Command Value Description Serial Error Number DescriptionSeed See also getchar, putchar, KBHit, ChangeBaud TestSuite Xprintf Monitor Standard Monitor Functions Acronyms Acronyms Acronyms Index Idma channels -4initialization Xsprintf Index FDL 10002367-02 E R S O N. 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