ZEUS Technical Manual | Detailed hardware description |
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PXA270 GPIO pin assignments
The table below summarizes the use of the 118 PXA270 GPIO pins, their direction, alternate function and active level.
Key:AF |
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Dir |
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Active | Function active level or edge. |
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| For details of pin states during sleep modes and reset see the Pin Usage table | |||||||||
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| in the Intel PXA27x Processor Family Electrical, Mechanical and Thermal | |||||||||
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| Specification. |
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| No | AF Signal name | Dir | Active Function | source | See section… | ||||||
0 | 0 | AC97_IRQ | Input |
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| AC97Interrupt | 3 | ||||
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1 | 0 | DS_WAKEUP | Input |
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| Reset in case of power | 3 |
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3 | 0 | PWR_SCL | Output |
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| PXA270 Power Manager I2C |
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4 | 0 | PWR_SDA | Bidir. |
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5 | N/A PWR_CAP0 | Power |
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6 | N/A PWR_CAP1 | Power |
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| achieve low power during |
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7 | N/A PWR_CAP2 | Power |
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8 | N/A PWR_CAP3 | Power |
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9 | 0 | UART_INTA | Input |
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| UART 1 Interrupt | ||
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10 | 0 | UART_INTB |
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| UART 2 Interrupt | ||
Input |
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11 | 0 | UART_INTD | Input |
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| UART 4 Interrupt | |||
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12 | 0 | UART_INTC | Input |
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| UART 3 Interrupt | ||
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Serial COM ports, page 53