ZEUS Technical Manual | Power and power management |
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Ethernet power management
The Ethernet controllers (Davicom DM9000A) incorporate a number of features to maintain the lowest power consumption.
The device can be put into a
The PHY can be put into a sleep mode by setting the PHY control register bit 16.1, which powers down all the circuits except the oscillator and clock generator circuit.
The PHY can be put into a
For more information about power management, refer to the DM9000A datasheet on the Development Kit CD.
Audio power management
The audio CODEC (Wolfson WM9712L) supports the standard power down control register defined by AC’97 standard (26h). In addition, the individual sections of the chip can be powered down through register 24h. Significant power savings can be achieved by disabling parts of WM9712L that are not used.
Shutting down all the clocks and digital and analogue sections can reduce WM9712L consumption down to near zero (1.65μW).
For more information about power management, refer to the WM9712L datasheet on the Development Kit CD.
LVDS power management
If not used, the DS90C363 LVDS transmitter can be placed in power down mode by applying a
CPU_ GPIO21 (LVDS_EN) | LVDS operation status |
0 | Power down mode |
1 | Normal operation |
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© 2007 Eurotech Ltd Issue D | 71 |