ZEUS Technical Manual

Detailed hardware description

 

 

Watchdog timer

The ZEUS uses an external watchdog timer (MAX6369) which can be used to protect against erroneous software. This is a programmable watchdog timer that can be adjusted for timeout periods of 1ms, 10ms, 30ms, 100ms, 1s, 10s and 60s. The board is reset when timeout occurs. The MAX6369 watchdog timer can be programmed using the WD setup register provided within the CPLD. The register is memory mapped (accessible through CS5#). The WDT is disabled upon reset, and remains so until enabled by the software.

The following table shows the WD setup register bit definitions:

Watchdog Register [REG3]

 

Bits

Description

7:4

Not used.

3

WDI: Watchdog Input. If WDI remains either high or low for the

 

 

duration of the watchdog timeout period (tWD), WDT triggers a reset

 

 

pulse. The internal watchdog timer clears whenever a reset pulse

 

 

is asserted or whenever WDI sees a rising or falling edge.

2:0

WDSET[2:0] – watchdog enable / timeout period setup bits.

 

 

Hex Offset Address:

0x13800000

Reset Hex Value:

0x03

Access:

Read/write

For further details, see the Intel PXA27x Processor Family Developer’s Manual on the Development Kit CD.

© 2007 Eurotech Ltd Issue D

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