Block Guide — S12EETX4KV0 V00.04
17
3.3 Register Descriptions

3.3.1 ECLKDIV — EEPROM Clock Divider Register

The ECLKDIV register is used to control timed events in program and erase algorithms.
Figure 3-2 EEPROM Clock Divider Register (ECLKDIV)
All bits in the ECLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable.
EDIVLD — Clock Divider Loaded.
1 = Register has been written to since the last reset.
0 = Register has not been written.
PRDIV8 — Enable Prescalar by 8.
1 = Enables a prescalar by 8, to divide the oscillator clock before feeding into the clock divider.
0 = The oscillator clock is directly fed into the ECLKDIV divider.
EDIV[5:0] — Clock Divider Bits.
Thecombination of PRDIV8 and EDIV[5:0] effectively divides the EEPROM module input oscillator
clock down to a frequency of 150kHz - 200kHz. The maximum divide ratio is 512. Please refer to
section 4.1.1 for more information.

3.3.2 RESERVED1

This register is reserved for factory testing and is not accessible.
Figure 3-3 RESERVED1
All bits read zero and are not writable.
Address Offset: $_00
76543210
REDIVLD PRDIV8 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0
W
RESET: 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Address Offset: $_01
76543210
R00000000
W
Reset: 00000000
= Unimplemented or Reserved
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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