Freescale Semiconductor Block Guide, EETX4K

Block Guide — S12EETX4KV0 V00.04

then 182kHz. In this case, the EEPROM program and erase algorithm timings are increased over the

optimum target by:

NOTE:

"4"Program and erase command execution time will increase proportionally with

the period of EECLK.

NOTE:

Because of the impact of clock synchronization on the accuracy of the functional

timings,programming or erasing the EEPROM memory cannot be performed if the

bus clock runs at less than 1 MHz. Programming or erasing the EEPROM memory

with EECLK < 150kHz should be avoided. Setting ECLKDIV to a value such that

EECLK < 150kHz can destroy the EEPROM memory due to overstress. Setting

ECLKDIV to a value such that (1/EECLK+Tbus) < 5µs can result in incomplete

programming or erasure of the EEPROM memory cells.

If the ECLKDIV register is written, the EDIVLD bit is set automatically. If the EDIVLD bit is zero, the

ECLKDIV register has not been written since the last reset. If the ECLKDIV register has not been written

to, the EEPROM command loaded during a command write sequence will not execute and the ACCERR

flag in the ESTAT register will set.

200 182–()200⁄100×9%=

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Freescale Semiconductor, Inc.

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