5.5 Ultra DMA Feature Set

13)The host shall neither negate STOP nor HSTROBE until at least tACK after negating DMACK-.

14)The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating DMACK.

5.5.5Ultra DMA CRC rules

The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command.

a)Both the host and the device shall have a 16-bit CRC calculation function.

b)Both the host and the device shall calculate a CRC value for each Ultra DMA burst.

c)The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of an Ultra DMA burst before any data is transferred.

d)For each STROBE transition used for data transfer, both the host and the device shall calculate a new CRC value by applying the CRC polynomial to the current value of their individual CRC functions and the word being transferred. CRC is not calculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged.

e)At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the device on DD (15:0) with the negation of DMACK-.

f)The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function. If the two values do not match, the device shall save the error and report it at the end of the command. A subsequent Ultra DMA burst for the same command that does not have a CRC error shall not clear an error saved from a previous Ultra DMa burst in the same command. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.

g)For READ DMA or WRITE DMA commands: When a CRC error is detected, it shall be reported by setting both ICRC and ABRT (bit 7 and bit 2 in the Error register) to one. ICRC is defined as the "Interface CRC Error" bit. The host shall respond to this error by re-issuing the command.

h)A host may send extra data words on the last Ultra DMA burst of a data out command. If a device determines that all data has been transferred for a command, the device shall terminate the burst. A device may have already received more data words than were required for the command. These extra words are used by both the host and the device to calculate the CRC, but, on an Ultra DMA data out burst, the extra words shall be discarded by the device.

i)The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1.

C141-E050-02EN

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Fujitsu MHC2032AT, MHD2021AT, MHC2040AT, MHD2032AT manual Ultra DMA CRC rules
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MHC2040AT, MHC2032AT, MHD2032AT, MHD2021AT specifications

Fujitsu offers a range of advanced hard disk drives (HDD) designed for various computing needs, including the MHD2021AT, MHD2032AT, MHC2032AT, and MHC2040AT models. These drives combine reliable performance, capacity options, and technological features aimed at enhancing data storage efficiency.

The Fujitsu MHD2021AT is known for its capacity of 20 GB, making it an excellent choice for users requiring a compact and efficient HDD. With a spindle speed of 5400 RPM, it balances speed and power consumption, catering to mobile computing and lower power devices. Its ATA interface ensures compatibility with a wide range of systems, making it a versatile option for various applications.

The MHD2032AT model offers a slightly higher capacity of 30 GB, maintaining similar technological attributes to its predecessor. With an enhanced data transfer rate, it allows for quicker access to stored files, perfect for users handling larger volumes of data. The robust error correction features in this model further ensure data integrity, making it a reliable choice for demanding environments.

For users needing more robust storage solutions, the MHC2032AT steps it up with features tailored for performance-heavy applications. Its 30 GB capacity is suited for desktop and workstation environments that require swift data retrieval and significant storage. The drive employs advanced caching techniques, which boost performance further by optimizing read and write operations, ensuring smoother multitasking capabilities.

The MHC2040AT is the flagship model in this line, providing an impressive storage capacity of 40 GB. This HDD is designed for high-performance applications where speed is crucial. The drive’s increased spindle speed and superior data transfer rates make it ideal for video editing, gaming, and large database management. Alongside its enhanced performance features, it includes advanced thermal management technology that maintains optimal operational temperatures, prolonging the drive's lifespan.

All four models leverage Fujitsu's commitment to data reliability, featuring robust shock resistance and low noise levels. Collectively, these drives cater to a spectrum of user needs, from compact data storage to high-capacity solutions, maintaining Fujitsu's reputation for quality and innovation in the storage market.
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