© Copyright IBM Cor p. 2001, 2002 9
Chapter 2. Architecture and technical overview

The following sections provide more detailed information about the architecture of the M odels

6C1 and 6E1. Figure 2-1 shows the high level system block diagram of both models.

Figure 2-1 Model 6C1 and 6E1 - high-level system block diagram

2
IntegratedService
Processor PCIBridge PCIBridge
External
Ultra3-SCSI
10/100
Ethernet
3rd serial
port Super
I/O
ISABridge
2PCISlots
32bit
33MHz
5v
2PCISlots
64-bit
50MH z
3.3v
System Planar
Data
Addr/Cntl
MemoryData Bus
Memory
Address 6xxData Bus
6xxAddress Bus
Memory
512M B - 8 GB
ProcessorCard
POWER3-II
333MHz,
375M Hz,or
450MHz
4MBL2
w/375 MH z
8MBL2
w/450 MH z
Processor Card
POWER3-II
4MBL2
w/375 MH z
8MBL2
w/450 MH z
SCSIController
Internal
Ultra3-SCSI
10/100
Ethernet
IDE
CD-
ROM
1PCISlots
64bit
33MHz
5v
16Bytes @ 93.75 MHz w/ 375 MHz
16Bytes @ 90.00 MHz w/ 450 MHz
16Bytes @ 93.75 MHz w/ 375 MHz
16Bytes @ 90.00 MHz w/ 450 MHz 6xx-MX Bus
66MHz
250MH z
w/375 MHz
225MH z
w/450 MHz
250M Hz
w/375 MHz
225M Hz
w/450 MHz
4MBL2
w/333 MH z
4MBL2
w/333 MH z
333MHz,
375M Hz,or
450MHz
166.5MHz
w/333 MHz
166.5MHz
w/333 MHz
16Bytes @ 95.14 MHz w/ 333 MHz
16Bytes @ 95.14 MHz w/ 333 MHz