Intel 253668-032US 4.5 IA-32E PAGING

Vol. 3 4-23
PAGING
that do neither because they are “not present”; bit 0 (P) and bit 7 (PS) are high-
lighted because they determine how a paging-structure entry is used.
4.5 IA-32E PAGING
A logical processor uses IA-32e paging if CR0.PG = 1, CR4.PAE = 1, and
IA32_EFER.LME = 1. With IA-32e paging, linear address are translated using a hier-
archy of in-memory paging structures located using the contents of CR3. IA-32e
paging translates 48-bit linear addresses to 52-bit physical addresses.1 Although 52
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1M1
NOTES:
1. M is an abbreviation for MAXPHYADDR.
M-1 3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
09876543210
Ignored2
2. CR3 has 64 bits only on processors supporting the Intel-64 architecture. These bits are ignored with
PAE paging.
Address of page-directory-pointer table Ignored CR3
Reserved3
3. Reserved fields must be 0.
Address of page directory Ign. Rsvd. P C
D
P
W
T
Rs
vd 1PDPTE:
present
Ignored 0PDTPE:
not
present
X
DIgnored Rsvd. Address of
2MB page frame Reserved P
A
TIgn. G 1DAP
C
D
P
W
T
U
/
S
R
/
W1PDE:
2MB
page
X
DIgnored Rsvd. Address of page table Ign. 0I
g
nAP
C
D
P
W
T
U
/
S
R
/
W1PDE:
page
table
Ignored 0PDE:
not
present
X
DIgnored Rsvd. Address of 4KB page frame Ign. G P
A
TDAP
C
D
P
W
T
U
/
S
R
/
W1PTE:
4KB
page
Ignored 0PTE:
not
present
Figure 4-7. Formats of CR3 and Paging-Structure Entries with PAE Paging