Vol. 3 11-5
MEMORY CACHE CONTROL
Intel 64 and IA-32 processors may implement four types of caches: the trace cache,
the level 1 (L1) cache, the level 2 (L2) cache, and the level 3 (L3) cache. See
Figure 11-1. Cache availability is described below:
•Intel Core i7 processor Family — The L1 cache is divided into two sections:
one section is dedicated to caching instructions (pre-decoded instructions) and
the other caches data. The L2 cache is a unified data and instruction cache. Each
processor core has its own L1 and L2. The L3 cache is an inclusive, unified data
and instruction cache, shared by all processor cores inside a physical package. No
trace cache is implemented.
•Intel Core 2 processor and Intel Xeon processor Family based on Intel
Core microarchitecture — The L1 cache is divided into two sections: one
section is dedicated to caching instructions (pre-decoded instructions) and the
other caches data. The L2 cache is a unified data and instruction cache located on
the processor chip; it is shared between two processor cores in a dual-core
processor implementation. Quad-core processors have two L2, each shared by
two processor cores. No trace cache is implemented.
•Intel Atom processor — The L1 cache is divided into two sections: one section
is dedicated to caching instructions (pre-decoded instructions) and the other
caches data. The L2 cache is a unified data and instruction cache is located on the
processor chip. No trace cache is implemented.
•Intel Core Solo and Intel Core Duo processors — The L1 cache is divided into
two sections: one section is dedicated to caching instructions (pre-decoded
instructions) and the other caches data. The L2 cache is a unified data and
instruction cache located on the processor chip. It is shared between two
processor cores in a dual-core processor implementation. No trace cache is
implemented.
Store Buffer • Intel Core i7 processors : 32entries.
• Intel Core 2 Duo processors: 20 entries.
• Intel Atom processors: 8 entries, used for both WC and store buffers.
• Pentium 4 and Intel Xeon processors: 24 entries.
• Pentium M processor: 16 entries.
•P6 family processors: 12 entries.
• Pentium processor: 2 buffers, 1 entry each (Pentium processors with
MMX technology have 4 buffers for 4 entries).
Write Combining
(WC) Buffer
• Intel Core 2 Duo processors: 8 entries.
• Intel Atom processors: 8 entries, used for both WC and store buffers.
• Pentium 4 and Intel Xeon processors: 6 or 8 entries.
• Intel Core Duo, Intel Core Solo, Pentium M processors: 6 entries.
• P6 family processors: 4 entries.
NOTES:
1 Introduced to the IA-32 architecture in the Pentium 4 and Intel Xeon processors.
Table 11-1. Characteristics of the Caches, TLBs, Store Buffer, and
Write Combining Buffer in Intel 64 and IA-32 Processors (Contd.)
Cache or Buffer Characteristics