Intel 253668-032US Table 6-8. SIMD Floating-Point Exceptions Priority

Vol. 3 6-65
INTERRUPT AND EXCEPTION HANDLING
Note that because SIMD floating-point exceptions are precise and occur immediately,
the situation does not arise where an x87 FPU instruction, a WAIT/FWAIT instruction,
or another SSE/SSE2/SSE3 instruction will catch a pending unmasked SIMD floating-
point exception.
In situations where a SIMD floating-point exception occurred while the SIMD
floating-point exceptions were masked (causing the corresponding exception flag to
be set) and the SIMD floating-point exception was subsequently unmasked, then no
exception is generated when the exception is unmasked.
When SSE/SSE2/SSE3 SIMD floating-point instructions operate on packed operands
(made up of two or four sub-operands), multiple SIMD floating-point exception
conditions may be detected. If no more than one exception condition is detected for
one or more sets of sub-operands, the exception flags are set for each exception
condition detected. For example, an invalid exception detected for one sub-operand
will not prevent the reporting of a divide-by-zero exception for another sub-operand.
However, when two or more exceptions conditions are generated for one sub-
operand, only one exception condition is reported, according to the precedences
shown in Table 6-8. This exception precedence sometimes results in the higher
priority exception condition being reported and the lower priority exception condi-
tions being ignored.
Exception Error Code
None.
Table 6-8. SIMD Floating-Point Exceptions Priority
Priority Description
1 (Highest) Invalid operation exception due to SNaN operand (or any NaN operand for
maximum, minimum, or certain compare and convert operations).
2QNaN operand1.
3Any other invalid operation exception not mentioned above or a divide-by-zero
exception2.
4Denormal operand exception2.
5Numeric overflow and underflow exceptions possibly in conjunction with the
inexact result exc eption2.
6 (Lowest) Inexact result exception .
NOTES:
1. Though a QNaN this is not an exception, the handling of a QNaN operand has precedence over
lower priority exceptions. For example, a QNaN divided by zero results in a QNaN, not a divide-
by-zero- exception.
2. If masked, then instruction execution continues, and a lower priority exception can occur as
well.