Intel 253668-032US Table 2-2. Summary of System Instructions (Contd.)

2-28 Vol. 3
SYSTEM ARCHITECTURE OVERVIEW
SLDT Store LDT Register No No
LGDT Load GDT Register No Yes
SGDT Store GDT Register No No
LTR Load Task Regist er No Yes
STR Store Task Register No No
LIDT Load IDT Register No Yes
SIDT Store IDT Register No No
MOV CRnLoad and store control registers No Yes
SMSW Store MSW Yes No
LMSW Load MSW No Yes
CLTS Clear TS flag in CR0 No Yes
ARPL Adjust RPL Yes1, 5 No
LAR Load Access Rights Yes No
LSL Load Segment Lim it Yes No
VERR Verify for Reading Ye s No
VERW Verify for Writing Yes No
MOV DRnLoad and store debug registers No Yes
INVD Invalidate cache, no writeback No Yes
WBINVD Invalidate cache, with writeback No Yes
INVLPG Invalidate TLB entry No Yes
HLT Halt Processor No Yes
LOCK (Prefi x) Bus Lock Yes No
RSM Return from system management
mode
No Yes
RDMSR3Read Model-Specific Re gisters No Ye s
WRMSR3Write Model-Specific Registers No Ye s
RDPMC4Read Performance-Monitoring
Counter
Yes Yes2
RDTSC3Read Time-Stamp Counter Yes Yes2
RDTSCP7Read Serialized Time-Stamp Counter Yes Yes2
Table 2-2. Summary of System Instructions (Contd.)
Instruction Description
Useful to
Application?
Protected from
Application?