Intel 253668-032US 6.10 INTERRUPT DESCRIPTOR TABLE (IDT)

6-12 Vol. 3
INTERRUPT AND EXCEPTION HANDLING
While priority among these classes listed in Table 6-2 is consistent throughout the
architecture, exceptions within each class are implementation-dependent and may
vary from processor to processor. The processor first services a pending exception or
interrupt from the class which has the highest priority, transferring execution to the
first instruction of the handler. Lower priority exceptions are discarded; lower priority
interrupts are held pending. Discarded exceptions are re-generated when the inter-
rupt handler returns execution to the point in the program or task where the excep-
tions and/or interrupts occurred.
6.10 INTERRUPT DESCRIPTOR TABLE (IDT)
The interrupt descriptor table (IDT) associates each exception or interrupt vector
with a gate descriptor for the procedure or task used to service the associated excep-
tion or interrupt. Like the GDT and LDTs, the IDT is an array of 8-byte descriptors (in
5Nonmaskable Interrupts (NMI) 1
6Maskable Hardware Interrupts 1
7Code Breakpoint Fault
8Faults from Fetching Next Instruction
- Code-Segment Limit Violation
- Code Page Fault
9Faults from Decoding the Next Instruction
- Instruction length > 15 bytes
- Invalid Opcode
- Coprocessor Not Available
10 (Lowest) Faults on Executing an Instruction
- Overflow
- Bound error
- Invalid TSS
- Segment Not Present
- Stack fault
- General Protection
- Data Page Fault
- Alignment Check
- x87 FPU Floating-point exception
- SIMD floating-point exception
NOTE:
1. The Intel486™ processor and earlier processors group nonmaskable and maskable interrupts in
the same priority class.
Table 6-2. Priority Among Simultaneous Exceptions and Interrupts (Contd.)