Intel 253668-032US Figure 2-6. Control Registers

Vol. 3 2-19
SYSTEM ARCHITECTURE OVERVIEW
When loading a control register, reserved bits should always be set to the values
previously read. The flags in control registers are:
PG Paging (bit 31 of CR0) — Enables paging when set; disables paging when
clear. When paging is disabled, all linear addresses are treated as physical
addresses. The PG flag has no effect if the PE flag (bit 0 of register CR0) is
not also set; setting the PG flag when the PE flag is clear causes a general-
protection exception (#GP). See also: Chapter 4, “Paging.”
On Intel 64 processors, enabling and disabling IA-32e mode operation also
requires modifying CR0.PG.
CD Cache Disable (bit 30 of CR0) — When the CD and NW flags are clear,
caching of memory locations for the whole of physical memory in the
processor’s internal (and external) caches is enabled. When the CD flag is
set, caching is restricted as described in Table 11-5. To prevent the processor
from accessing and updating its caches, the CD flag must be set and the
caches must be invalidated so that no cache hits can occur.
Figure 2-6. Control Registers
CR1
W
P
A
M
Page-Directory Base
V
M
E
P
S
E
T
S
D
D
E
P
V
I
P
G
E
M
C
E
P
A
E
P
C
E
N
W
P
GC
D
P
W
T
P
C
D
Page-Fault Linear Address
P
E
E
MM
P
T
S
N
EE
T
CR2
CR0
CR4
Reserved
CR3
Reserved (set to 0)
31 29 30 28 1918 17 16 15 6543210
31(63) 0
31(63) 0
31(63) 1211 5432
31(63) 9876543210
(PDBR)
13 12 1110
OSFXSR
OSXMMEXCPT
V
M
X
E
00
E
X
M
S
14
18
OSXSAVE