6-34 Vol. 3
INTERRUPT AND EXCEPTION HANDLING
Interrupt 6—Invalid Opcode Exception (#UD)
Exception Class Fault.
Description
Indicates that the processor did one of the following things:
•Attempted to execute an invalid or reserved opcode.
•Attempted to execute an instruction with an operand type that is invalid for its
accompanying opcode; for example, the source operand for a LES instruction is
not a memory location.
•Attempted to execute an MMX or SSE/SSE2/SSE3 instruction on an Intel 64 or
IA-32 processor that does not support the MMX technology or
SSE/SSE2/SSE3/SSSE3 extensions, respectively. CPUID feature flags MMX (bit
23), SSE (bit 25), SSE2 (bit 26), SSE3 (ECX, bit 0), SSSE3 (ECX, bit 9) indicate
support for these extensions.
•Attempted to execute an MMX instruction or SSE /SSE2/SSE3/SSSE3 SIMD
instruction (with the exception of the MOVNTI, PAUSE, PREFETCHh, SFENCE,
LFENCE, MFENCE, CLFLUSH, MONITOR, and MWAIT instructions) when the EM
flag in control register CR0 is set (1).
•Attempted to execute an SSE/SE2/SSE3/SSSE3 instruction when the OSFXSR bit
in control register CR4 is clear (0). Note this does not include the following
SSE/SSE2/SSE3 instructions: MASKMOVQ, MOVNTQ, MOVNTI, PREFETCHh,
SFENCE, LFENCE, MFENCE, and CLFLUSH; or the 64-bit versions of the PAVGB,
PAVGW, PEXTRW, PINSRW, PMAXSW, PMAXUB, PMINSW, PMINUB, PMOVMSKB,
PMULHUW, PSADBW, PSHUFW, PADDQ, PSUBQ, PAL IGNR, P ABSB, P ABSD ,
PABSW, PHADDD, PHADDSW , PHADDW, PHSUBD, PHSUBSW, PHSUBW,
PMADDUBSM, PMULHRSW, PSHUFB, PSIGNB, PSIGND, and PSIGNW.
•Attempted to execute an SSE/SSE2/SSE3/SSSE3 instruction on an Intel 64 or
IA-32 processor that caused a SIMD floating-point exception when the
OSXMMEXCPT bit in control register CR4 is clear (0).
•Executed a UD2 instruction. Note that even though it is the execution of the UD2
instruction that causes the invalid opcode exception, the saved instruction
pointer will still points at the UD2 instruction.
•Detected a LOCK prefix that precedes an instruction that may not be locked or
one that may be locked but the destination operand is not a memory location.
•Attempted to execute an LLDT, SLDT, LTR, STR, LSL, LAR, VERR, VERW, or ARPL
instruction while in real-address or virtual-8086 mode.
•Attempted to execute the RSM instruction when not in SMM mode.
In Intel 64 and IA-32 processors that implement out-of-order execution microarchi-
tectures, this exception is not generated until an attempt is made to retire the result
of executing an invalid instruction; that is, decoding and speculatively attempting to
execute an invalid opcode does not generate this exception. Likewise, in the Pentium