Vol. 3 15-23
MACHINE-CHECK ARCHITECTURE
•Write 7FFFH to IA32_MCi_CTL2[15:0],
•Read back IA32_MCi_CTL2[15:0], the lower 15 bits (14:0) is the
maximum threshold supported by the processor.
b. Increase the threshold to a value below the maximum value discovered using
step a.

15.5.2.3 CMCI Interrupt Handler

The following describes techniques system software may consider to imple-
ment a CMCI service routine:
•The service routine examines its private per-thread data structure to check which
set of MC banks it has ownership. If the thread does not have ownership of a
given MC bank, proceed to the next MC bank. Ownership is determined at initial-
ization time which is described in Section [Cross Reference to 14.5.2.1].
•If the thread had claimed ownership to an MC bank,
— Check for valid MC errors by testing IA32_MCi_STATUS.VALID[63],
•Log MC errors,
•Clear the MSRs of this MC bank.
— If no valid error, proceed to next MC bank.
•When all MC banks have been processed, exit service routine and return to
original program execution.
This technique will allow each logical processors to handle corrected MC
errors independently and requires no synchronization to access shared MSR
resources.
15.6 RECOVERY OF UNCORRECTED RECOVERA BLE (UCR) ERRORS
Recovery of uncorrected recoverable machine check errors is an enhance-
ment in machine-check architecture. The first processor that supports this
feature is 45nm Intel 64 processor with CPUID signature
DisplayFamily_DisplayModel encoding of 06H_2EH. This allow system soft-
ware to perform recovery action on certain class of uncorrected errors and
continue execution.