Intel 80219 specifications Problem

Intel® 80219 General Purpose PCI Processor

Core Errata

11.Performance Monitor Unit Event 0x1 Can Be Incremented Erroneously by Unrelated Events

Problem:	Event 0x1 in the performance monitor unit (PMU) can be used to count cycles in which the
	instruction cache cannot deliver an instruction. The only cycles counted should be those due to an
	instruction cache miss or an instruction TLB miss. The following unrelated events in the core, also
	causes the corresponding count to increment when event number 0x1 is being monitored:

1.Any architectural event (e.g. IRQ, data abort)

2.MSR instructions which alter the CPSR control bits

3.Some branch instructions, including indirect branches and those mispredicted by the BTB

4.CP15 mcr instructions to registers 7, 8, 9, or 10 which involve the instruction cache or the instruction TLB.

Each of the items above may cause the performance monitoring count to increment several times. The resulting performance monitoring count may be higher than expected when the above items occur, but never lower.

Workaround: There is no way to obtain the correct number of cycles stalled due to instruction cache misses and instruction TLB misses. Extra counts due to branch instructions mispredicted by the BTB, may be one component of the unwanted count that can be filtered out. The number of mispredicted branches can also be monitored using performance monitoring event 0x6 during the same time period as event 0x1. The mispredicted branch number can then be subtracted from the instruction cache stall number generated by the performance monitor to get a value closer to the correct one. Note that this only addresses counts contributed by branches that the BTB is able to predict. All the items listed above still affect the count. Depending on the nature of the code being monitored, this workaround may have limited value.

Status: NoFix.

12.In Special Debug State, Back-to-Back Memory Operations Where the First Instruction Aborts May Cause a Hang

Problem:	When back-to-back memory operations occur in the Special Debug State (SDS, used by ICE and
	Debug vendors) and the first memory operation gets a precise data abort, the first memory
	operation is correctly cancelled and no abort occurs. However, depending on the timing, the second
	memory operation may not work correctly. The data cache may internally cancel the second
	operation, but the register file may have score-boarded registers for that second memory operation.
	The effect is that the core may hang (due to a permanently score-boarded register) or that a store
	operation may be incorrectly cancelled.
Workaround:	In Special Debug State, any memory operation that may cause a precise data abort should be
	followed by a write-buffer drain operation. This precludes further memory operations from being
	in the pipe when the abort occurs. Load Multiple/Store Multiple that may cause precise data aborts
	should not be used.
Status:	NoFix.

Specification Update 17