
Intel® 80219 General Purpose PCI Processor
Summary Table of Changes
Core Errata
No. | Steppings | Page | Status | Errata | |
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1 | X | 13 | NoFix | Boundary Scan Is Not Fully Compliant to the IEEE 1149.1 Specification | |
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2 | X | 13 | NoFix | Drain Is Not Flushed Correctly when Stalled in the Pipeline | |
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3 | X | 14 | NoFix | Undefined Data | |
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4 | X | 14 | NoFix | Debug Unit Synchronization with the TXRXCTRL Register | |
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5 | X | 14 | NoFix | Extra Circuitry Is Not JTAG Boundary Scan Compliant | |
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6 | X | 15 | NoFix | Incorrect Decode of Unindexed Mode, Using Addressing Mode 5, Can Corrupt Protected | |
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7 | X | 15 | NoFix | Load Immediately Following a DMM Flush Entry is Also Flushed | |
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8 | X | 15 | NoFix | Trace Buffer Does Not Operate Below 1.3 V | |
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9 | X | 15 | NoFix | Data Cache Unit Can Stall for a Single Cycle | |
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10 | X | 16 | NoFix | Aborted Store that Hits the Data Cache May Mark Writeback Data As Dirty | |
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11 | X | 17 | NoFix | Performance Monitor Unit Event 0x1 Can Be Incremented Erroneously by Unrelated | |
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12 | X | 17 | NoFix | In Special Debug State, | |
Aborts May Cause a Hang | |||||
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13 | X | 18 | NoFix | Accesses to the CP15 ID register with opcode2 > 0b001 returns unpredictable values | |
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14 | X | 18 | NoFix | Disabling and | |
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15 | X | 19 | NoFix | Updating the JTAG parallel register requires an extra TCK rising edge | |
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8 | Specification Update |