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Specs
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Intel
®
80219 General Purpose PCI Processor
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Specification Update
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Contents
Intel 80219 General Purpose PCI Processor
Specification Update
Contents
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Revision History
Affected Documents/Related Documents
Preface
Nomenclature
Summary Table of Changes
Codes Used in Summary Table
Core Errata
Steppings Status Errata
Non-Core Errata
FRAME#
Specification Clarifications
Specification Changes
Documentation Changes
Identification Information
Markings
Die Details
Drain Is Not Flushed Correctly when Stalled in the Pipeline
Core Errata
Debug Unit Synchronization with the Txrxctrl Register
Extra Circuitry Is Not Jtag Boundary Scan Compliant
Trace Buffer Does Not Operate Below 1.3
Data Cache Unit Can Stall for a Single Cycle
Core Errata
Operation may be incorrectly cancelled
Disabling the MMU or re-enabling it afterwards
Core Errata
PBI Issue When Using 16-bit PBI Transactions in PCI Mode
Non-Core Errata
Continues running the counter
MCU supports a page size of 2 Kbytes for 64-bit mode
Vih Minimum Input High Voltage Vih level for the PCI pins
Specification Changes
Gpio Output Data Register address = Ffff E7CCh
Controller
Specification Clarifications
Application note Hot-Debug for Intel Xscale Core Debug
BAR0 Configuration When Using the Messaging Unit MU
Reading Unpopulated Sdram Memory Banks
Writing to reserved registers can cause unexpected behavior
Not completed out of order
Documentation Changes
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