About This
| System Bus | The System Bus is the microprocessor bus of the processor. |
| Setup Window | The time between the beginning of Setup to Clock (TSU_MIN) |
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| and the arrival of a valid clock edge. This window may be |
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| different for each type of bus agent in the system. |
| SSO | Simultaneous Switching Output (SSO) effects are differences in |
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| electrical timing parameters and degradation in signal quality |
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| caused by multiple signal outputs simultaneously switching |
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| voltage levels in the opposite direction from a single signal or in |
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| the same direction. These are called odd mode and even mode |
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| switching, respectively. This simultaneous switching of multiple |
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| outputs creates higher current swings that may cause additional |
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| propagation delay |
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| delay |
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| or hold times and are not always taken into account by |
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| simulations. System timing budgets should include margin for |
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| SSO effects. |
| Stub | The branch from the bus trunk terminating at the pad of an |
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| agent. |
| Trunk | The main connection, excluding interconnect branches, from |
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| one end agent pad to the other end agent pad. |
| Undershoot | The minimum voltage extending below VSS observed for a |
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| signal at the device pad. |
| VCC (CPU core) | VCC (CPU core) is the core power for the processor. The system |
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| bus is terminated to VCC (CPU core). |
| Victim | A network that receives a coupled crosstalk signal from another |
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| network is called the victim network. |
| VRD 10.0 | The Voltage Regulator Module (a down on the board solution) |
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| specification for the Intel® Pentium® 4 Processor with HT |
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| Technology processor. It is a |
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| supplies the required voltage and current to a single processor. |
| Table 1 defines the acronyms used throughout this document. | |
Table 1. | Acronyms (Sheet 1 of 2) | |
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| Acronym | Definition |
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| AC | Audio Codec |
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| ASF | Alert Standard Format |
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| AMC | Audio/Modem Codec. |
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| Any | |
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| CMC | Common Mode Choke |
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| CNR | Communications and Networking Riser |
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| EMI | Electro Magnetic Interference |
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| ESD | Electrostatic Discharge |
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| FS | |
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| HS | |
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| ICH | I/O Controller Hub |
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| LOM | LAN on Motherboard |
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| LPC | Low Pin Count |
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| Mobile Intel® 915GME Express Chipset |
April 2007 | Development Kit User’s Manual |
Order Number: | 11 |