Technical Reference

Table 12. I/O Map (continued)

Address (hex)

Size

Description

96 contiguous bytes starting on a

ICH (ACPI + TCO)

128-byte divisible boundary

 

64 contiguous bytes starting on a

Onboard resource

64-byte divisible boundary

 

32 contiguous bytes starting on a

ICH (USB)

32-byte divisible boundary

 

16 contiguous bytes starting on a

16-byte divisible boundary

4096 contiguous bytes starting on a 4096-byte divisible boundary

ICH (SMBus)

Intel 82810EAA PCI Bridge

32 contiguous bytes starting on a

Intel 82559 LAN Controller

32-byte divisible boundary

 

96 contiguous bytes starting on a

LPC47M102 PME Status

128-byte divisible boundary

 

64 contiguous bytes starting on a Creative ES1373D Digital Audio Controller 64-byte divisible boundary

Notes:

1.Default, but can be changed to another address range

2.Dword access only

3.Byte access only

NOTE

Some additional I/O addresses are not available due to ICH addresses aliasing. For information about ICH addressing, refer to Intel web site at:

http://developer.intel.com/design/chipsets/datashts/

2.4 DMA Channels

Table 13. DMA Channels

DMA Channel Number

Data Width

System Resource

0

8- or 16-bits

Audio

1

8- or 16-bits

Audio

2

8- or 16-bits

Open

3

8- or 16-bits

Open / Audio

4

 

Reserved - cascade channel

5

16-bits

Open

6

16-bits

Open

7

16-bits

Open

 

 

 

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