Technical Reference

2.7 PCI Interrupt Routing Map

This section describes interrupt sharing and how the interrupt signals are connected between the PCI bus connector and onboard PCI devices. The PCI specification specifies how interrupts can be shared between devices attached to the PCI bus. In most cases, the small amount of latency added by interrupt sharing does not affect the operation or throughput of the devices. In some special cases where maximum performance is needed from a device, a PCI device should not share an interrupt with other PCI devices. Use the following information to avoid sharing an interrupt with a PCI add-in card.

PCI devices are categorized as follows to specify their interrupt grouping:

∙INTA: By default, all add-in cards that require only one interrupt are in this category. For almost all cards that require more than one interrupt, the first interrupt on the card is also classified as INTA.

∙INTB: Generally, the second interrupt on add-in cards that require two or more interrupts is classified as INTB. (This is not an absolute requirement.)

∙INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a fourth interrupt is classified as INTD.

The ICH PCI-to-LPC bridge has four programmable interrupt request (PIRQ) input signals. Any PCI interrupt source (either onboard or from a PCI add-in card) connects to one of these

PIRQ signals. Because there are only four signals, some PCI interrupt sources are mechanically tied together on the board and therefore share the same interrupt. Table 16 lists the PIRQ signals and shows how the signals are connected to the PCI bus connectors and to onboard PCI interrupt sources.

Table 16. PCI Interrupt Routing Map

PCI Interrupt Source

 

ICH PIRQ Signal Name

 

PIRQA

PIRQB

PIRQC

PIRQD

 

AGP Controller

INTA

 

 

 

ICH Audio Controller

 

 

INTC

 

ICH USB Controller

 

 

 

INTD

Intel 82559 PCI LAN Controller

 

 

INTC

 

PCI Bus Connector

INTA

INTB

INTC

INTD

✏NOTE

The ICH can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 10, 11, 14, and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ lines to be connected to the same IRQ signal.

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