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CONTENTS FOR VOLUME 3A AND 3B
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FIGURES
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TABLES
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CHAPTER 1 ABOUT THIS MANUAL
1.1 IA-32 PROCESSORS COVERED IN THIS MANUAL
1.2 OVERVIEW OF THE SYSTEM PROGRAMMING GUIDE
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1.3 NOTATIONAL CONVENTIONS
1.3.1 Bit and Byte Order
1.3.2 Reserved Bits and Software Compatibility
1.3.3 Instruction Operands
1.3.4 Hexadecimal and Binary Numbers
1.3.5 Segmented Addressing
1.3.6 Syntax for CPUID, CR, and MSR Values
1.3.7 Exceptions
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CHAPTER 2 SYSTEM ARCHITECTURE OVERVIEW
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Figure 2-1. IA-32 System-Level Registers and Data Structures
Figure 2-2. System-Level Registers and Data Structures in IA-32e Mode
2.1.1 Global and Local Descriptor Tables
2.1.2 System Segments, Segment Descriptors, and Gates
2.1.3 Task-State Segments and Task Gates
2.1.4 Interrupt and Exception Handling
2.1.5 Memory Management
2.1.6 System Registers
2.2 MODES OF OPERATION
System Management Mode
2.3 SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER
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2.3.1 System Flags and Fields in IA-32e Mode
2.4 MEMORY-MANAGEMENT REGISTERS
2.4.1 Global Descriptor Table Register (GDTR)
2.4.2 Local Descriptor Table Register (LDTR)
2.4.3 IDTR Interrupt Descriptor Table Register
2.4.4 Task Register (TR)
2.5 CONTROL REGISTERS
2-18 Vol. 3A
Page-Directory Base
(PDBR)
Figure 2-6. Control Registers
CR1
Page-Fault Linear Address
CR2
CR4
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2.5.1 CPUID Qualification of Control Register Flags
2.6 SYSTEM INSTRUCTION SUMMARY
2.6.1 Loading and Storing System Registers
2.6.2 Verifying of Access Privileges
2.6.3 Loading and Storing Debug Registers
2.6.4 Invalidating Caches and TLBs
2.6.5 Controlling the Processor
2.6.6 Reading Performance-Monitoring and Time-Stamp Counters
2.6.7 Reading and Writing Model-Specific Registers
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CHAPTER 3 PROTECTED-MODE MEMORY MANAGEMENT
3.1 MEMORY MANAGEMENT OVERVIEW
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3.2 USING SEGMENTS
3.2.1 Basic Flat Model
3.2.2 Protected Flat Model
Figure 3-2. Flat Model
Figure 3-3. Protected Flat Model
3.2.3 Multi-Segment Model
3.2.4 Segmentation in IA-32e Mode
3.2.5 Paging and Segmentation
3.3 PHYSICAL ADDRESS SPACE
3.3.1 Physical Address Space for Processors with Intel EM64T
3.4 LOGICAL AND LINEAR ADDRESSES
3.4.1 Logical Address Translation in IA-32e Mode
3.4.2 Segment Selectors
3.4.3 Segment Registers
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3.4.4 Segment Loading Instructions in IA-32e Mode
3.4.5 Segment Descriptors
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Table 3-1. Code- and Data-Segment Types
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3.5 SYSTEM DESCRIPTOR TYPES
3.5.1 Segment Descriptor Tables
Figure 3-10. Global and Local Descriptor Tables
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3.5.2 Segment Descriptor Tables in IA-32e Mode
3.6 PAGING (VIRTUAL MEMORY) OVERVIEW
3.6.1 Paging Options
3.6.2 Page Tables and Directories in the Absence of Intel EM64T
3.7.1 Linear Address Translation (4-KByte Pages)
Figure 3-12. Linear Address Translation (4-KByte Pages)
Table 3-3. Page Sizes and Physical Address Sizes
3.7.2 Linear Address Translation (4-MByte Pages)
3.7.3 Mixing 4-KByte and 4-MByte Pages
3.7.4 Memory Aliasing
3.7.5 Base Address of the Page Directory
3.7.6 Page-Directory and Page-Table Entries
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3.7.7 Not Present Page-Directory and Page-Table Entries
3.8 36-BIT PHYSICAL ADDRESSING USING THE PAE PAGING MECHANISM
3.8.1 Enhanced Legacy PAE Paging
3.8.2 Linear Address Translation With PAE Enabled (4-KByte Pages)
3.8.3 Linear Address Translation With PAE Enabled (2-MByte Pages)
3.8.4 Accessing the Full Extended Physical Address Space With the Extended Page-Table Structure
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Vol. 3A 3-35
Page-Directory Entry (4-KByte Page Table)
Page-Table Base Address
Page-Table Entry (4-KByte Page)
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3.9 36-BIT PHYSICAL ADDRESSING USING THE PSE-36 PAGING MECHANISM
Figure 3-22. Linear Address Translation (4-MByte Pages)
Figure 3-23. Format of Page-Directory Entries for 4-MByte Pages and 36-Bit Physical Addresses
3.10 PAE-ENABLED PAGING IN IA-32E MODE
3.10.1 IA-32e Mode Linear Address Translation (4-KByte Pages)
3.10.2 IA-32e Mode Linear Address Translation (2-MByte Pages)
3.10.3 Enhanced Paging Data Structures
3-42 Vol. 3A
Figure 3-26. Format of Paging Structure Entries for 4-KByte Pages in IA-32e Mode
levels.
Page-Directory Entry (4-KByte Page Table)
Page-Table Base Address
Page-Table Entry (4-KByte Page)
Table 3-4. Reserved Bit Checking When Execute Disable Bit is Disabled
Table 3-5. Reserved Bit Checking When Execute Disable Bit is Enabled
3.11 MAPPING SEGMENTS TO PAGES
3.12 TRANSLATION LOOKASIDE BUFFERS (TLBS)
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CHAPTER 4 PROTECTION
4.1 ENABLING AND DISABLING SEGMENT AND PAGE PROTECTION
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PROTECTION
Figure 4-1. Descriptor Fields Used for Protection
4.2.1 Code Segment Descriptor in 64-bit Mode
4.3 LIMIT CHECKING
4.3.1 Limit Checking in 64-bit Mode
4.4 TYPE CHECKING
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4.4.1 Null Segment Selector Checking
4.5 PRIVILEGE LEVELS
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4.6 PRIVILEGE LEVEL CHECKING WHEN ACCESSING DATA SEGMENTS
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4.6.1 Accessing Data in Code Segments
4.7 PRIVILEGE LEVEL CHECKING WHEN LOADING THE SS REGISTER
4.8 PRIVILEGE LEVEL CHECKING WHEN TRANSFERRING PROGRAM CONTROL BETWEEN CODE SEGMENTS
4.8.1 Direct Calls or Jumps to Code Segments
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4.8.2 Gate Descriptors
4.8.3 Call Gates
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PROTECTION
Figure 4-10. Call-Gate Mechanism
Figure 4-11. Privilege Check for Control Transfer with Call Gate
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4.8.5 Stack Switching
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4.8.6 Returning from a Called Procedure
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4.8.7 Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions
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4.10.1 Checking Access Rights (LAR Instruction)
4.10.2 Checking Read/Write Rights (VERR and VERW Instructions)
4.10.3 Checking That the Pointer Offset Is Within Limits (LSL Instruction)
4.10.4 Checking Caller Access Privileges (ARPL Instruction)
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4.10.5 Checking Alignment
4.11 PAGE-LEVEL PROTECTION
4.11.1 Page-Protection Flags
4.11.2 Restricting Addressable Domain
4.11.3 Page Type
4.12 COMBINING PAGE AND SEGMENT PROTECTION
4.13 PAGE-LEVEL PROTECTION AND EXECUTE-DISABLE BIT
4.13.1 Detecting and Enabling the Execute-Disable Bit Capability
4.13.2 Execute-Disable Bit Page Protection
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4.13.3 Reserved Bit Checking
4.13.4 Exception Handling
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CHAPTER 5 INTERRUPT AND EXCEPTION HANDLING
5.1 INTERRUPT AND EXCEPTION OVERVIEW
5.2 EXCEPTION AND INTERRUPT VECTORS
5.3 SOURCES OF INTERRUPTS
5.3.1 External Interrupts
Table 5-1. Protected-Mode Exceptions and Interrupts
5.3.2 Maskable Hardware Interrupts
5.3.3 Software-Generated Interrupts
5.4 SOURCES OF EXCEPTIONS
5.4.1 Program-Error Exceptions
5.4.2 Software-Generated Exceptions
5.4.3 Machine-Check Exceptions
5.5 EXCEPTION CLASSIFICATIONS
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5.7 NONMASKABLE INTERRUPT (NMI)
5.7.1 Handling Multiple NMIs
5.8 ENABLING AND DISABLING INTERRUPTS
5.8.1 Masking Maskable Hardware Interrupts
5.8.2 Masking Instruction Breakpoints
5.8.3 Masking Exceptions and Interrupts When Switching Stacks
5.9 PRIORITY AMONG SIMULTANEOUS EXCEPTIONS AND INTERRUPTS
Table 5-2. Priority Among Simultaneous Exceptions and Interrupts
5.10 INTERRUPT DESCRIPTOR TABLE (IDT)
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5.11 IDT DESCRIPTORS
5.12 EXCEPTION AND INTERRUPT HANDLING
Figure 5-2. IDT Gate Descriptors
5.12.1 Exception- or Interrupt-Handler Procedures
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5.12.2 Interrupt Tasks
Figure 5-5. Interrupt Task Switch
5.13 ERROR CODE
5.14 EXCEPTION AND INTERRUPT HANDLING IN 64-BIT MODE
5.14.1 64-Bit Mode IDT
5.14.2 64-Bit Mode Stack Frame
5.14.3 IRET in IA-32e Mode
5.14.4 Stack Switching in IA-32e Mode
5.14.5 Interrupt Stack Table
5.15 EXCEPTION AND INTERRUPT REFERENCE
Interrupt 0Divide Error Exception (#DE)
Interrupt 1Debug Exception (#DB)
Interrupt 2NMI Interrupt
Interrupt 3Breakpoint Exception (#BP)
Interrupt 4Overflow Exception (#OF)
Interrupt 5BOUND Range Exceeded Exception (#BR)
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Interrupt 7Device Not Available Exception (#NM)
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Interrupt 8Double Fault Exception (#DF)
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Interrupt 9Coprocessor Segment Overrun
Interrupt 10Invalid TSS Exception (#TS)
Table 5-6. Invalid TSS Conditions
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Interrupt 11Segment Not Present (#NP)
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Interrupt 12Stack Fault Exception (#SS)
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Interrupt 14Page-Fault Exception (#PF)
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Interrupt 16x87 FPU Floating-Point Error (#MF)
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Interrupt 17Alignment Check Exception (#AC)
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Interrupt 18Machine-Check Exception (#MC)
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Interrupt 19SIMD Floating-Point Exception (#XF)
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Interrupts 32 to 255User Defined Interrupts
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CHAPTER 6 TASK MANAGEMENT
6.1 TASK MANAGEMENT OVERVIEW
6.1.1 Task Structure
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6.1.3 Executing a Task
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Figure 6-2. 32-Bit Task-State Segment (TSS)
registers prior to the task switch.
and EDI registers prior to the task switch.
6.2.2 TSS Descriptor
6.2.3 TSS Descriptor in 64-bit mode
6.2.4 Task Register
Figure 6-4. Format of TSS and LDT Descriptors in 64-bit Mode
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6.2.5 Task-Gate Descriptor
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6.4 TASK LINKING
Figure 6-8. Nested Tasks
Table 6-2. Effect of a Task Switch on Busy Flag, NT Flag, Previous Task Link Field, and TS Flag
6.4.1 Use of Busy Flag To Prevent Recursive Task Switching
6.4.2 Modifying Task Linkages
6.5 TASK ADDRESS SPACE
6.5.1 Mapping Tasks to the Linear and Physical Address Spaces
6.5.2 Task Logical Address Space
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Figure 6-10. 16-Bit TSS Format
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Figure 6-11. 64-Bit TSS Format
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CHAPTER 7 MULTIPLE-PROCESSOR MANAGEMENT
7.1 LOCKED ATOMIC OPERATIONS
7.1.1 Guaranteed Atomic Operations
7.1.2 Bus Locking
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7.1.3 Handling Self- and Cross-Modifying Code
7.1.4 Effects of a LOCK Operation on Internal Processor Caches
7.2 MEMORY ORDERING
7.2.1 Memory Ordering in the Intel Pentium and Intel486
7.2.2 Memory Ordering Pentium 4, Intel Xeon, and P6 Family
7.2.3 Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors
7.2.4 Strengthening or Weakening the Memory Ordering Model
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7.3 PROPAGATION OF PAGE TABLE AND PAGE DIRECTORY ENTRY CHANGES TO MULTIPLE PROCESSORS
7.4 SERIALIZING INSTRUCTIONS
7.5 MULTIPLE-PROCESSOR (MP) INITIALIZATION
7.5.1 BSP and AP Processors
7.5.2 MP Initialization Protocol Requirements and Restrictions for Intel Xeon Processors
7.5.3 MP Initialization Protocol Algorithm for Intel Xeon Processors
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7.5.5 Identifying Logical Processors in an MP System
7.6 HYPER-THREADING AND MULTI-CORE TECHNOLOGY
7.7 DETECTING HARDWARE MULTI-THREADING SUPPORT AND TOPOLOGY
7.7.1 Initializing IA-32 Processors Supporting Hyper-Threading Technology
7.7.2 Initializing Dual-Core IA-32 Processors
7.7.3 Executing Multiple Threads on an IA-32 Processor Supporting Hardware Multi-Threading
7.7.4 Handling Interrupts on an IA-32 Processor Supporting Hardware Multi-Threading
MULTIPLE-PROCESSOR MANAGEMENT
Figure 7-3. Local APICs and I/O APIC in MP System Supporting HT Technology
7.8 INTEL HYPER-THREADING TECHNOLOGY ARCHITECTURE
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7.8.4 Page Attribute Table (PAT)
7.8.5 Machine Check Architecture
7.8.6 Debug Registers and Extensions
7.8.7 Performance Monitoring Counters
7.8.8 IA32_MISC_ENABLE MSR
7.8.9 Memory Ordering
7.8.10 Serializing Instructions
7.8.11 MICROCODE UPDATE Resources
7.8.12 Self Modifying Code
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7.9 DUAL-CORE ARCHITECTURE
7.9.1 Logical Processor Support
7.9.2 Memory Type Range Registers (MTRR)
7.9.3 Performance Monitoring Counters
7.9.4 IA32_MISC_ENABLE MSR
7.9.5 MICROCODE UPDATE Resources
7.10 PROGRAMMING CONSIDERATIONS FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
7.10.2 Identifying Logical Processors in an MP System
MULTIPLE-PROCESSOR MANAGEMENT
7.10.3 Algorithm for Three-Level Mappings of APIC_ID
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7.10.4 Identifying Topological Relationships in a MP System
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7.11 MANAGEMENT OF IDLE AND BLOCKED CONDITIONS
7.11.1 HLT Instruction
7.11.2 PAUSE Instruction
7.11.3 Detecting Support MONITOR/MWAIT Instruction
7.11.4 MONITOR/MWAIT Instruction
7.11.5 Monitor/Mwait Address Range Determination
7.11.6 Required Operating System Support
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CHAPTER 8 ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
8.1 LOCAL AND I/O APIC OVERVIEW
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8.2 SYSTEM BUS VS. APIC BUS
8.3 THE INTEL 82489DX EXTERNAL APIC, THE APIC, AND THE XAPIC
8.4 LOCAL APIC
8.4.1 The Local APIC Block Diagram
Figure 8-4. Local APIC Structure
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8.4.2 Presence of the Local APIC
Table 8-1. Local APIC Register Address Map (Contd.)
8.4.3 Enabling or Disabling the Local APIC
8.4.4 Local APIC Status and Location
8.4.5 Relocating the Local APIC Registers
8.4.6 Local APIC ID
8.4.7 Local APIC State
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8.4.8 Local APIC Version Register
8.5 HANDLING LOCAL INTERRUPTS
8.5.1 Local Vector Table
Figure 8-8. Local Vector Table (LVT)
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8.5.2 Valid Interrupt Vectors
8.5.3 Error Handling
8.5.4 APIC Timer
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8.5.5 Local Interrupt Acceptance
8.6 ISSUING INTERPROCESSOR INTERRUPTS
8.6.1 Interrupt Command Register (ICR)
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Table 8-4. Valid Combinations for the P6 Family Processors Local APIC Interrupt Command Register
8.6.2 Determining IPI Destination
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8.6.3 IPI Delivery and Acceptance
8.7 SYSTEM AND APIC BUS ARBITRATION
8.8 HANDLING INTERRUPTS
8.8.1 Interrupt Handling with the Pentium 4 and Intel Xeon
8.8.2 Interrupt Handling with the P6 Family and Pentium
Vol. 3A 8-35
Figure 8-17. Interrupt Acceptance Flow Chart for the Local APIC (P6 Family and Pentium Processors)
8.8.3 Interrupt, Task, and Processor Priority
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8.8.4 Interrupt Acceptance for Fixed Interrupts
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8.8.5 Signaling Interrupt Servicing Completion
8.8.6 Task Priority in IA-32e Mode
8.9 SPURIOUS INTERRUPT
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8.10 APIC BUS MESSAGE PASSING MECHANISM AND PROTOCOL (P6 FAMILY, PENTIUM PROCESSORS)
8.10.1 Bus Message Formats
8.11 MESSAGE SIGNALLED INTERRUPTS
8.11.1 Message Address Register Format
8.11.2 Message Data Register Format
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CHAPTER 9 PROCESSOR MANAGEMENT AND INITIALIZATION
9.1 INITIALIZATION OVERVIEW
9.1.1 Processor State After Reset
9.1.2 Processor Built-In Self-Test (BIST)
Table 9-1. IA-32 Processor States Following Power-up, Reset, or INIT
Table 9-1. IA-32 Processor States Following Power-up, Reset, or INIT (Contd.)
9.1.3 Model and Stepping Information
Figure 9-2. Version Information in the EDX Register after Reset
Figure 9-1. Contents of CR0 Register after Reset
9.1.4 First Instruction Executed
9.2 X87 FPU INITIALIZATION
9.2.1 Configuring the x87 FPU Environment
9.2.2 Setting the Processor for x87 FPU Software Emulation
9.3 CACHE ENABLING
9.4 MODEL-SPECIFIC REGISTERS (MSRS)
9.5 MEMORY TYPE RANGE REGISTERS (MTRRS)
9.6 INITIALIZING SSE/SSE2/SSE3 EXTENSIONS
9.7 SOFTWARE INITIALIZATION FOR REAL-ADDRESS MODE OPERATION
9.7.1 Real-Address Mode IDT
9.7.2 NMI Interrupt Handling
9.8 SOFTWARE INITIALIZATION FOR PROTECTED-MODE OPERATION
9.8.1 Protected-Mode System Data Structures
9.8.2 Initializing Protected-Mode Exceptions and Interrupts
9.8.3 Initializing Paging
9.8.4 Initializing Multitasking
9.8.5 Initializing IA-32e Mode
9.9 MODE SWITCHING
9.9.1 Switching to Protected Mode
9.9.2 Switching Back to Real-Address Mode
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9.10 INITIALIZATION AND MODE SWITCHING EXAMPLE
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9.10.1 Assembler Usage
9.10.2 STARTUP.ASM Listing
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Figure 9-5. Moving the GDT, IDT, and TSS from ROM to RAM (Lines 196-261 of List File)
Figure 9-6. Task Switching (Lines 282-296 of List File)
9.10.3 MAIN.ASM Source Code
9.10.4 Supporting Files
Table 9-5 shows the relationship of each build item with an ASM source file.
9.11 MICROCODE UPDATE FACILITIES
Table 9-5. Relationship Between BLD Item and ASM Source File
9.11.1 Microcode Update
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Table 9-6. Microcode Update Field Definitions (Contd.)
Table 9-7. Microcode Update Format
Table 9-6. Microcode Update Field Definitions (Contd.)
9.11.2 Optional Extended Signature Table
9.11.3 Processor Identification
9.11.4 Platform Identification
9.11.5 Microcode Update Checksum
9.11.6 Microcode Update Loader
9.11.7 Update Signature and Verification
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9.11.8 Pentium 4, Intel Xeon, and P6 Family Processor Microcode Update Specifications
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Table 9-12. Microcode Update Functions
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Figure 9-8. Microcode Update Write Operation Flow [1]
Vol. 3A 9-59
Figure 9-9. Microcode Update Write Operation Flow [2]
9-60 Vol. 3A
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Table 9-17. Parameters for the Read Microcode Update Data Function
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CHAPTER 10 MEMORY CACHE CONTROL
10.1 INTERNAL CACHES, TLBS, AND BUFFERS
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10.2 CACHING TERMINOLOGY
10.3 METHODS OF CACHING AVAILABLE
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10.3.1 Buffering of Write Combining Memory Locations
10.3.2 Choosing a Memory Type
10.4 CACHE CONTROL PROTOCOL
10.5 CACHE CONTROL
10.5.1 Cache Control Registers and Bits
Figure 10-2. Cache-Control Registers and Bits Available in IA-32 Processors
Table 10-5. Cache Operating Modes
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10.5.2 Precedence of Cache Controls
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10.5.3 Preventing Caching
10.5.4 Disabling and Enabling the L3 Cache
10.5.5 Cache Management Instructions
10.5.6 L1 Data Cache Context Mode
10.6 SELF-MODIFYING CODE
10.7 IMPLICIT CACHING (PENTIUM 4, INTEL XEON, AND P6 FAMILY PROCESSORS)
10.8 EXPLICIT CACHING
10.9 INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS (TLBS)
10.10 STORE BUFFER
10.11 MEMORY TYPE RANGE REGISTERS (MTRRS)
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10.11.1 MTRR Feature Identification
10.11.2 Setting Memory Ranges with MTRRs
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Figure 10-6 shows flags and fields in these registers. The functions of these flags and fields are:
for the encoding of this field).
Table 10-9. Address Mapping for Fixed-Range MTRRs
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10.11.3 Example Base and Mask Calculations
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10.11.4 Range Size and Alignment Requirement
10.11.5 MTRR Initialization
10.11.6 Remapping Memory Types
10.11.7 MTRR Maintenance Programming Interface
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10.11.8 MTRR Considerations in MP Systems
10.11.9 Large Page Size Considerations
10.12 PAGE ATTRIBUTE TABLE (PAT)
10.12.1 Detecting Support for the PAT Feature
10.12.2 IA32_CR_PAT MSR
10.12.3 Selecting a Memory Type from the PAT
10.12.4 Programming the PAT
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10.12.5 PAT Compatibility with Earlier IA-32 Processors
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CHAPTER 11 INTEL MMX TECHNOLOGY SYSTEM PROGRAMMING
11.1 EMULATION OF THE MMX INSTRUCTION SET
11.2 THE MMX STATE AND MMX REGISTER ALIASING
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11.2.1 Effect of MMX, x87 FPU, FXSAVE, and FXRSTOR Instructions on the x87 FPU Tag Word
11.3 SAVING AND RESTORING THE MMX STATE AND REGISTERS
11.4 SAVING MMX STATE ON TASK OR CONTEXT SWITCHES
11.5. EXCEPTIONS THAT CAN OCCUR WHEN EXECUTING MMX INSTRUCTIONS
11.5.1 Effect of MMX Instructions on Pending x87 Floating-Point Exceptions
11.6 DEBUGGING MMX CODE
INTEL MMX TECHNOLOGY SYSTEM PROGRAMMING
Figure 11-2. Mapping of MMX Registers to x87 FPU Data Register Stack
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CHAPTER 12 SSE, SSE2 AND SSE3 SYSTEM PROGRAMMING
12.1 PROVIDING OPERATING SYSTEM SUPPORT FOR SSE/SSE2/SSE3 EXTENSIONS
12.1.1 Adding Support to an Operating System for SSE/SSE2/SSE3 Extensions
12.1.2 Checking for SSE/SSE2/SSE3 Extension Support
12.1.3 Checking for Support for the FXSAVE and FXRSTOR Instructions
12.1.4 Initialization of the SSE/SSE2/SSE3 Extensions
12.1.6 Providing an Handler for the SIMD Floating-Point Exception (#XF)
12.2 EMULATION OF SSE/SSE2/SSE3 EXTENSIONS
12.3 SAVING AND RESTORING THE SSE/SSE2/SSE3 STATE
12.4 SAVING THE SSE/SSE2/SSE3 STATE ON TASK OR CONTEXT SWITCHES
12.5.1. Using the TS Flag to Control the Saving of the x87 FPU, MMX, SSE, SSE2 and SSE3 State
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CHAPTER 13 POWER AND THERMAL MANAGEMENT
13.1 ENHANCED INTEL SPEEDSTEP TECHNOLOGY
13.1.1 Software Interface For Initiating Performance State Transitions
13.2 P-STATE HARDWARE COORDINATION
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13.3 MWAIT EXTENSIONS FOR ADVANCED POWER MANAGEMENT
13.4 THERMAL MONITORING AND PROTECTION
13.4.1 Catastrophic Shutdown Detector
13.4.2 Thermal Monitor
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13.4.3 Software Controlled Clock Modulation
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13.4.4 Detection of Thermal Monitor and Software Controlled Clock Modulation Facilities
13.4.5 On Die Digital Thermal Sensors
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CHAPTER 14 MACHINE-CHECK ARCHITECTURE
14.1 MACHINE-CHECK EXCEPTIONS AND ARCHITECTURE
14.2 COMPATIBILITY WITH PENTIUM PROCESSOR
14.3 MACHINE-CHECK MSRS
14.3.1 Machine-Check Global Control MSRs
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14.3.2 Error-Reporting Register Banks
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MACHINE-CHECK ARCHITECTURE
Table 14-2. Extended Machine Check State MSRs In Processors With Support For Intel EM64T
Table 14-1. Extended Machine Check State MSRs in Processors Without Support for EM64T (Contd.)
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14.3.3 Mapping of the Pentium Processor Machine-Check Errors to the Machine-Check Architecture
14.4 MACHINE-CHECK AVAILABILITY
14.5 MACHINE-CHECK INITIALIZATION
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14.6. INTERPRETING THE MCA ERROR CODES
14.6.1 Simple Error Codes
14.6.2 Compound Error Codes
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14.6.3 Machine-Check Error Codes Interpretation
14.7 GUIDELINES FOR WRITING MACHINE-CHECK SOFTWARE
14.7.1 Machine-Check Exception Handler
14.7.2 Enabling BINIT# Drive and BINIT# Observation
14.7.3 Pentium Processor Machine-Check Exception Handling
14.7.4 Logging Correctable Machine-Check Errors
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CHAPTER 15 8086 EMULATION
15.1 REAL-ADDRESS MODE
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15.1.1 Address Translation in Real-Address Mode
15.1.2 Registers Supported in Real-Address Mode
15.1.3 Instructions Supported in Real-Address Mode
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15.1.4 Interrupt and Exception Handling
15.2 VIRTUAL-8086 MODE
Table 15-1. Real-Address Mode Exceptions and Interrupts
15.2.1 Enabling Virtual-8086 Mode
15.2.2 Structure of a Virtual-8086 Task
15.2.3 Paging of Virtual-8086 Tasks
Figure 15-3. Entering and Leaving Virtual-8086 Mode
15.2.6 Leaving Virtual-8086 Mode
15.2.7 Sensitive Instructions
15.2.8 Virtual-8086 Mode I/O
15.3 INTERRUPT AND EXCEPTION HANDLING IN VIRTUAL-8086 MODE
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15.3.1 Class 1Hardware Interrupt and Exception Handling in Virtual-8086 Mode
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15.3.3 Class 3Software Interrupt Handling in Virtual-8086 Mode
Table 15-2. Software Interrupt Handling Methods While in Virtual-8086 Mode
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15.4 PROTECTED-MODE VIRTUAL INTERRUPTS
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CHAPTER 16 MIXING 16-BIT AND 32-BIT CODE
16.1 DEFINING 16-BIT AND 32-BIT PROGRAM MODULES
16.2 MIXING 16-BIT AND 32-BIT OPERATIONS WITHIN A CODE SEGMENT
16.3 SHARING DATA AMONG MIXED-SIZE CODE SEGMENTS
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16.4.1 Code-Segment Pointer Size
16.4.2 Stack Management for Control Transfer
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16.4.3 Interrupt Control Transfers
16.4.4 Parameter Translation
16.4.5 Writing Interface Procedures
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CHAPTER 17 IA-32 ARCHITECTURE COMPATIBILITY
17.1. IA-32 PROCESSOR FAMILIES AND CATEGORIES
17.2. RESERVED BITS
17.3. ENABLING NEW FUNCTIONS AND MODES
17.5. INTEL MMX TECHNOLOGY
17.6. STREAMING SIMD EXTENSIONS (SSE)
17.7. STREAMING SIMD EXTENSIONS 2 (SSE2)
17.8. STREAMING SIMD EXTENSIONS 3 (SSE3)
17.9. HYPER-THREADING TECHNOLOGY
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17.15.1 Using EFLAGS Flags to Distinguish Between 32-Bit IA-32
17.16. STACK OPERATIONS
17.16.1 PUSH SP
17.16.2 EFLAGS Pushed on the Stack
17.17. X87 FPU
17.17.1 Control Register CR0 Flags
17.17.2 x87 FPU Status Word
17.17.3 x87 FPU Control Word
17.17.4 x87 FPU Tag Word
17.17.5 Data Types
17.17.6 Floating-Point Exceptions
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17.17.7 Changes to Floating-Point Instructions
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17.17.8 Transcendental Instructions
17.17.9 Obsolete Instructions
17.17.10WAIT/FWAIT Prefix Differences
17.17.11Operands Split Across Segments and/or Pages
17.17.12FPU Instruction Synchronization
17.18. SERIALIZING INSTRUCTIONS
17.19. FPU AND MATH COPROCESSOR INITIALIZATION
17.19.1 Intel387 and Intel287 Math Coprocessor Initialization
17.19.2 Intel486 SX Processor and Intel 487 SX Math Coprocessor Initialization
17.20. CONTROL REGISTERS
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17.21. MEMORY MANAGEMENT FACILITIES
17.21.1 New Memory Management Control Flags
17.21.2 CD and NW Cache Control Flags
17.21.3 Descriptor Types and Contents
17.21.4 Changes in Segment Descriptor Loads
17.22. DEBUG FACILITIES
17.22.1 Differences in Debug Register DR6
17.22.2 Differences in Debug Register DR7
17.22.3 Debug Registers DR4 and DR5
17.23. RECOGNITION OF BREAKPOINTS
17.24. EXCEPTIONS AND/OR EXCEPTION CONDITIONS
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17.25.3 IDT Limit
17.26. ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
17.26.1 Software Visible Differences Between the Local APIC and the 82489DX
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17.27.1 P6 Family and Pentium Processor TSS
17.27.2 TSS Selector Writes
17.27.3 Order of Reads/Writes to the TSS
17.27.4 Using A 16-Bit TSS with 32-Bit Constructs
17.27.5 Differences in I/O Map Base Addresses
17.28. CACHE MANAGEMENT
17.28.1 Self-Modifying Code with Cache Enabled
17.28.2 Disabling the L3 Cache
17.29. PAGING
17.29.1 Large Pages
17.29.2 PCD and PWT Flags
17.29.3 Enabling and Disabling Paging
17.30. STACK OPERATIONS
17.30.1 Selector Pushes and Pops
17.30.2 Error Code Pushes
17.30.3 Fault Handling Effects on the Stack
17.30.4 Interlevel RET/IRET From a 16-Bit Interrupt or Call Gate
17.31. MIXING 16- AND 32-BIT SEGMENTS
17.32. SEGMENT AND ADDRESS WRAPAROUND
17.33. STORE BUFFERS AND MEMORY ORDERING
17.34. BUS LOCKING
17.35. BUS HOLD
17.36. MODEL-SPECIFIC EXTENSIONS TO THE IA-32
17.36.1 Model-Specific Registers
17.36.2 RDMSR and WRMSR Instructions
17.36.3 Memory Type Range Registers
17.36.4 Machine-Check Exception and Architecture
17.36.5 Performance-Monitoring Counters
17.37. TWO WAYS TO RUN INTEL 286 PROCESSOR TASKS
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