Intel IA-32 manual TABLES

CONTENTS
xxx Vol. 3A
PAGE
Figure 18-23. MSR_IFSB_CTL6, Address: 107D2H;
MSR_IFSB_CNTR7, Address: 107D3H. . . . . . . . . . . . . . . . . . . . . . . . . . . .18-70
Figure 18-24. PerfEvtSel0 and PerfEvtSel1 MSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-71
Figure 18-25. CESR MSR (Pentium Processor Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-75
Figure 19-1. Interaction of a Virtual-Machine Monitor and Guests . . . . . . . . . . . . . . . . . . .14-3
Figure 19-1. CPUID Extended Feature Information ECX . . . . . . . . . . . . . . . . . . . . . . . . . .14-4
Figure 24-1. SMRAM Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-6
Figure 24-2. SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-17
Figure 24-3. Auto HALT Restart Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-18
Figure 24-4. SMBASE Relocation Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-19
Figure 24-5. I/O Instruction Restart Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-20
Figure 25-1. VMX Transitions and States of VMCS in a Logical Processor. . . . . . . . . . . . 23-4
Figure 26-1. Virtual TLB Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-6
Figure 27-1. Host External Interrupts and Guest Virtual Interrupts. . . . . . . . . . . . . . . . . . .25-6
Figure C-1. MP System With Multiple Pentium III Processors. . . . . . . . . . . . . . . . . . . . . . C-3
TABLES
Table 2-1. Action Taken By x87 FPU Instructions for Different
Combinations of EM, MP, and TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-20
Table 2-2. Summary of System Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-24
Table 3-1. Code- and Data-Segment Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15
Table 3-2. System-Segment and Gate-Descriptor Types . . . . . . . . . . . . . . . . . . . . . . . .3-17
Table 3-3. Page Sizes and Physical Address Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-23
Table 3-4. Reserved Bit Checking When Execute Disable Bit is Disabled . . . . . . . . . . .3-44
Table 3-5. Reserved Bit Checking When Execute Disable Bit is Enabled. . . . . . . . . . . .3-44
Table 4-1. Privilege Check Rules for Call Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-22
Table 4-2. 64-Bit-Mode Stack Layout After CALLF with CPL Change. . . . . . . . . . . . . . .4-26
Table 4-3. Combined Page-Directory and Page-Table Protection. . . . . . . . . . . . . . . . . .4-40
Table 4-4. Page Sizes and Physical Address Sizes Supported by
Execute-Disable Bit Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-41
Table 4-5. Extended Feature Enable MSR (IA32_EFER) . . . . . . . . . . . . . . . . . . . . . . . .4-41
Table 4-6. IA-32e Mode Page Level Protection Matrix
with Execute-Disable Bit Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-42
Table 4-7. Legacy PAE-Enabled 4-KByte Page Level Protection Matrix
with Execute-Disable Bit Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-42
Table 4-8. Legacy PAE-Enabled 2-MByte Page Level Protection
with Execute-Disable Bit Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-42
Table 4-9. IA-32e Mode Page Level Protection Matrix
with Execute-Disable Bit Capability Enabled . . . . . . . . . . . . . . . . . . . . . . . . .4-43
Table 4-10. Reserved Bit Checking WIth Execute-Disable Bit Capability
Not Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-44
Table 5-1. Protected-Mode Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
Table 5-2. Priority Among Simultaneous Exceptions and Interrupts . . . . . . . . . . . . . . . .5-11
Table 5-3. Debug Exception Conditions and Corresponding Exception Classes . . . . . . 5-28
Table 5-4. Interrupt and Exception Classes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-37
Table 5-5. Conditions for Generating a Double Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
Table 5-6. Invalid TSS Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-40
Table 5-7. Alignment Requirements by Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-57
Table 5-8. SIMD Floating-Point Exceptions Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-62