Intel IA-32 5.12 EXCEPTION AND INTERRUPT HANDLING

5-14 Vol. 3A
INTERRUPT AND EXCEPTION HANDLING
5.12 EXCEPTION AND INTERRUPT HANDLING
The processor handles calls to exception- and interrupt-handlers similar to the way it handles
calls with a CALL instruction to a procedure or a task. When responding to an exception or inter-
rupt, the processor uses the exception or interrupt vector as an index to a descriptor in the IDT.
If the index points to an interrupt gate or trap gate, the processor calls the exception or interrupt
handler in a manner similar to a CALL to a call gate (see Section 4.8.2, “Gate Descriptors,”
Figure 5-2. IDT Gate Descriptors
31 1615 13
14 12 870
P
Offset 31..16 D
P
L04
31 1615 0
Segment Selector Offset 15..0 0
011D
Interrupt Gate
DPL
Offset
P
Selector
Descriptor Privilege Level
Offset to procedure entry point
Segment Present flag
Segment Selector for destination code segment
31 1615 13
14 12 870
PD
P
L04
31 1615 0
TSS Segment Selector 0
1010
Task Gate
45
0 0 0
31 1615 13
14 12 87 0
P
Offset 31..16 D
P
L04
31 1615 0
Segment Selector Offset 15..0 0
111D
Trap Gat e
45
0 0 0
Reserved
Size of gate: 1 = 32 bits; 0 = 16 bitsD