Intel IA-32 MULTIPLE-PROCESSOR MANAGEMENT

Vol. 3A 7-37
MULTIPLE-PROCESSOR MANAGEMENT
Table 7-2 shows the initial APIC IDs for a hypothetical situation with a dual processor system.
Each physical package providing two processor cores, and each processor core also supporting
Hyper-Threading Technology.
Table 7-1. Initial APIC IDs for the Logical Processors in a System that has Four MP-Type
Intel Xeon Processors Supporting Hyper-Threading Technology 1
Initial APIC ID of Logical
Processor Package ID Core ID SMT ID
0H 0H 0H 0H
1H 0H 0H 1H
2H 1H 0H 0H
3H 1H 0H 1H
4H 2H 0H 0H
5H 2H 0H 1H
6H 3H 0H 0H
7H 3H 0H 1H
NOTE:
1. Because information on the number of processor cores in a physical package was not available in early
single-core processors supporting Hyper-Threading Technology, the core ID can be treated as 0.
Table 7-2. Initial APIC IDs for the Logical Processors in a System that has Two Physical
Processors Supporting Dual-Core and Hyper-Threading Technology
Initial APIC ID of a Logical
Processor Package ID Core ID SMT ID
0H 0H 0H 0H
1H 0H 0H 1H
2H 0H 1H 0H
3H 0H 1H 1H
4H 1H 0H 0H
5H 1H 0H 1H
6H 1H 1H 0H
7H 1H 1H 1H