Intel IA-32 Figure 10-2. Cache-Control Registers and Bits Available in IA-32 Processors

10-12 Vol. 3A
MEMORY CACHE CONTROL
Figure 10-2. Cache-Control Registers and Bits Available in IA-32 Processors
Page-Directory or
Page-Table Entry
TLBs
MTRRs3
Physical Memory
0
FFFFFFFFH2
control overall caching
of system memory
CD and NW Flags PCD and PWT flags
control page-level
caching
G flag controls page-
level flushing of TLBs
MTRRs control caching
of selected regions of
physical memory
P
C
D
CR3
Control caching of
page directory
P
W
T
C
D
CR0
N
W
Store Buffer
P
C
D
P
W
T
G1
CR4
Enables global pages
P
G
E
designated with G flag
1. G flag only available in Pentium 4, Intel Xeon, and P6 family
3. MTRRs available only in Pentium 4 and P6 family processors;
similar control available in Pentium processor with the KEN#
and WB/WT# pins.
2. The maximum physical address size is reported by CPUID leaf
function 80000008H. The maximum physical address size of
PAT4
PAT controls caching
of virtual memory
pages
4. PAT available only in Pentium III and Pentium 4 processors.
P4
A
T
processors.
IA32_MISC_ENABLE MSR
3rd Level
Cache Disable
FFFFFFFFFH applies only If 36-bit physical addressing is used.