Vol. 3A 3-43
PROTECTED-MODE MEMORY MANAGEMENT
The base physical address field in each entry is extended to 28 bits if the processor’s

implementation supports a 40-bit physical address.

Bits 62:52 are available for use by system programmers.
Bit 63 is the execute-disable bit if the execute-disable bit feature is supported in the

processor. If the feature is not supported, bit 63 is reserved. The functionality of the

execute disable bit is described in Section 4.11, “Page-Level Protection”. It requires both

PAE and enhanced paging data structures. Note that the execute disable bit can provide

page protection in 32-bit PAE mode and IA-32e mode.

3.10.3.1 Reserved Bit Checking

On processors supporting Intel EM64T and/or supporting the execute disable bit, the processor

will enforce reserved bit checking on paging mode specific bits.

Table 3-4 shows the reserved bits that are checked on IA-32 processors that support Intel

EM64T and when execute disable bit is either disabled or not supported. The 32-bit mode

behavior in Table 3-4 also applies to IA-32 processors that the support execute-disable bit but

not Intel EM64T.

Figure 3-27. Format of Paging Structure Entries for 2-MByte Pages in IA-32e Mode

63 62 32
Base
Reserved (set to 0)
Page-Directory-Pointer-Table Entry
31 1211 9 854320
P
C
D
P
W
T
Avail
Page-Directory Base Address
Addr.
Rsvd
63 62 52
32
Page Base
Reserved (set to 0)
Page-Directory Entry (2-MByte Page)
31 21 20 13 1211 98 7 6 5 4 3 2 1 0
P
C
DP
P
W
T
Page Base Address
G1 A R
/
W
U
/
S
Avail
P
1
63 62 32
Base
Reserved (set to 0)
Page-Map-Level-4-Table Entry
31 1211 9854320
P
C
D
P
W
T
Avail
PML4 Base Address
Addr.
Rsvd.
P
1
39
Avail
E
X
B
51
39
Avail
E
X
B
51
R
/
W
U
/
S
39
Avail
E
X
B
51
6
A
6
AR
/
W
U
/
S
Addr,
P
A
T
Reserved (set to 0)
D