3-42 Vol. 3A
PROTECTED-MODE MEMORY MANAGEMENT

Except for bit 63, functions of the flags in these entries are as described in Section 3.7.6, “Page-

Directory and Page-Table Entries”. The differences are:

A PML4 table entry and a page-directory-pointer-table entry are added.
Entries are increased from 32 bits to 64 bits.
The maximum number of entries in a page directory, page table, or PML4 table is 512.
The P, R/W, U/S, PWT, PCD, and A flags are implemented uniformly across all four

levels.

Figure 3-26. Format of Paging Structure Entries for 4-KByte Pages in IA-32e Mode

63 32
Base
Reserved (set to 0)
Page-Directory-Pointer-Table Entry
31 1211 9854320
P
C
D
P
W
T
Avail
Page-Directory Base Address
Addr.
Rsvd
63 32
Base
Reserved (set to 0)
Page-Directory Entry (4-KByte Page Table)
31 1211 9876543210
P
C
0DP
P
W
T
Page-Table Base Address
Addr.
00 A R
/
W
U
/
S
63 32
Base
Reserved (set to 0)
Page-Table Entry (4-KByte Page)
31 1211 9876543210
P
C
DDP
P
W
T
Page Base Address
Addr.
GA R
/
W
U
/
S
Avail
Avail
P
1
P
A
T
63 32
Base
Reserved (set to 0)
Page-Map-Level-4-Table Entry
31 1211 9854320
P
C
D
P
W
T
Avail
PML4 Base Address
Addr.
Rsvd.
P
1
3962
Avail
E
X
B
51
3962
Avail
E
X
B
51
3962
Avail
E
X
B
51
R
/
W
U
/
S
3962
Avail
E
X
B
51
6
A
6
AR
/
W
U
/
S