Intel IA-32 10.5.3 Preventing Caching

10-18 Vol. 3A
MEMORY CACHE CONTROL
10.5.2.3 Writing Values Across Pages with Different Memory Types
If two adjoining pages in memory have different memory types, and a word or longer operand
is written to a memory location that crosses the page boundary between those two pages, the
operand might be written to memory twice. This action does not present a problem for writes to
actual memory; however, if a device is mapped the memory space assigned to the pages, the
device might malfunction.
10.5.3 Preventing Caching
To disable the L1, L2, and L3 caches after they have been enabled and have received cache fills,
perform the following steps:
1. Enter the no-fill cache mode. (Set the CD flag in control register CR0 to 1 and the NW flag
to 0.
2. Flush all caches using the WBINVD instruction.
WB UC UC2
UC- UC2
WC WC
WT WT
WB WB
WP WP
WP UC UC2
UC- WC3
WC WC
WT WT3
WB WP
WP WP
NOTES:
1. The UC attribute comes from the MTRRs and the processors are not required to snoop their caches
since the data could never have been cached. This attribute is preferred for performance reasons.
2. The UC attribute came from the page-table or page-directory entry and processors are required to check
their caches because the data may be cached due to page aliasing, which is not recommended.
3. These combinations were specified as “undefined” in previous editions of the IA-32 Intel® Architecture
Software Developer’s Manual. However, all processors that support both the PAT and the MTRRs deter-
mine the effective page-level memory types for these combinations as given.
Table 10-7. Effective Page-Level Memory Types for Pentium III, Pentium 4,
and Intel Xeon Processors (Contd.)
MTRR Memory Type PAT Entry Value Effective Memory Type