10-6 Vol. 3A
MEMORY CACHE CONTROL
NOTE
The behavior of FP and SSE/SSE2 operations on operands in UC memory is
implementation dependent. In some implementations, accesses to UC
memory may occur more than once. To ensure predictable behavior, use loads
and stores of general purpose registers to access UC memory that may have
read or write side effects.
•Uncacheable (UC-) — Has same characteristics as the strong uncacheable (UC) memory
type, except that this memory type can be overridden by programming the MTRRs for the
WC memory type. This memory type is available in the Pentium 4, Intel Xeon, and
Pentium III processors and can only be selected through the PAT.
•Write Combining (WC) — System memory locations are not cached (as with
uncacheable memory) and coherency is not enforced by the processor’s bus coherency
protocol. Speculative reads are allowed. Writes may be delayed and combined in the write
combining buffer (WC buffer) to reduce memory accesses. If the WC buffer is partially
filled, the writes may be delayed until the next occurrence of a serializing event; such as,
an SFENCE or MFENCE instruction, CPUID execution, a read or write to uncached
memory, an interrupt occurrence, or a LOCK instruction execution. This type of cache-
control is appropriate for video frame buffers, where the order of writes is unimportant as
long as the writes update memory so they can be seen on the graphics display. See Section
10.3.1, “Buffering of Write Combining Memory Locations,” for more information about
caching the WC memory type. This memory type is available in the Pentium Pro and
Pentium II processors by programming the MTRRs or in the Pentium III, Pentium 4, and
Intel Xeon processors by programming the MTRRs or by selecting it through the PAT.
•Write-through (WT) — Writes and reads to and from system memory are cached. Reads
come from cache lines on cache hits; read misses cause cache fills. Speculative reads are
allowed. All writes are written to a cache line (when possible) and through to system
Table 10-2. Memory Types and Their Properties
Memory Type and
Mnemonic Cacheable Writeback
Cacheable Allows
Speculative
Reads
Memory Ordering Model
Strong Uncacheable
(UC) No No No Strong Ordering
Uncacheable (UC-) No No No Strong Ordering. Can only be
selected through the PAT. Can
be overridden by WC in MTRRs.
Write Combining (WC) No No Yes Weak Ordering. Available by
programming MTRRs or by
selecting it through the PAT.
Write Through (WT) Yes No Yes Speculative Processor Ordering.
Write Back (WB) Yes Yes Yes Speculative Processor Ordering.
Write Protected (WP) Yes for
reads; no for
writes
No Yes Speculative Processor Ordering.
Available by programming
MTRRs.