Intel Xeon, 6300ESB ICH user manual Products Feature List, Product Overview

Models: 6300ESB ICH Xeon

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1.3Products Feature List

Product Overview

1.3Products Feature List

Processor Support

Dual Intel® Xeon™ Processors

On-board processor voltage regulators compatible with VRM/EVRD 10.1 Design Guide

Clocking

CK409B clock synthesizer that generates all host clock and the PCI Express* interface clock for the MCH PHY Layer

DB800 generates the PCI Express differential pair clocks to the onboard PCI Express components and the dedicated PCI Express slots

Memory Support

Registered, ECC, DDR2 400

Each of the two memory channels on the Intel® E7520 in this CRB supports a maximum of two DDR2 400 DIMMs per channel

The maximum supported DDR2 400 memory configuration is 8 Gbyte using different combinations of single and dual ranked, x4, 1 Gbyte technology DIMMs (limit of up to four ranks per channel)

3.2 Gbytes/s bus per channel bandwidth with DDR2 400

I/O slot support

One PCI-X 133 MHz slot from PXH

Two PCI-X 100 MHz slots from PXH

One PCI Express x8 slot

One PCI Express x4 slot

One 5 V PCI-32/33 slot connected through the Intel® 6300ESB I/O Controller

Two 3.3 V PCI-X 64/66 slots connected through the Intel® 6300ESB I/O Controller

Low Pin Count Bus

National* LPC 47M172 Super I/O residing on LPC bus

LPC card header for debug purposes only

Firmware hub

IDE ATA 100 support

Two ATA-100 IDE connectors supported

S-ATA support

Two S-ATA connectors

USB Support (Four Channels)

Two USB 2.0 connectors

Two USB 2.0 headers

Back Panel I/O

8Intel® Xeon™ Processor, Intel® E7520 Chipset, Intel® 6300ESB ICH Development Kit User’s Manual

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Intel Xeon, 6300ESB ICH user manual Products Feature List, Product Overview