Intel Xeon, 6300ESB ICH user manual Platform Clocking, Clock Block Diagram

System Overview

5.2Platform Clocking

Figure 6.

SMA

￿$￿￿￿￿￿￿￿

The CRB uses one CK409B Clock Synthesizer to generate the host differential pair clocks and the
100 MHz differential clock to the DB800. The DB800 then generates the 100 MHz differential pair
￿￿￿￿￿￿￿￿￿
clock for the PCI Express* devices. Figure 6 shows the CRB clock configuration.
￿￿￿￿￿￿￿￿￿		CPU0
Clock Block Diagram
￿￿		ITP		￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿		DDRA
￿￿￿￿￿￿￿￿		CPU1		￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿
￿￿￿￿￿￿￿￿￿$	$￿￿￿￿￿￿￿￿￿￿￿		Intel￿			X-	￿￿￿￿
￿￿￿￿￿￿￿￿￿￿￿￿￿			I/O		￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿	DDRB
￿￿￿￿￿￿￿￿￿￿￿￿￿			MCH					PCI-X
￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿
			￿￿￿￿￿￿￿￿￿		￿￿￿￿PCI			PCI-X
								￿￿￿￿￿￿￿￿￿￿! ￿!￿￿￿￿￿￿
			6300ESB				￿￿￿￿￿￿￿￿￿￿￿￿￿
!￿￿￿￿￿￿￿￿￿￿			Controller			￿￿￿￿￿￿￿￿￿￿
			Hub
￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿					￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿￿			PXH
%&￿￿￿￿￿￿￿￿￿￿￿"￿￿#!￿￿		HI￿￿￿LAI$￿￿￿￿￿				#￿￿￿	!'￿
￿￿￿￿￿$￿￿￿￿￿￿￿			SIO
			Video			￿￿￿￿￿￿￿￿￿￿		PCI Express Slot
						￿￿￿￿￿#￿￿￿￿!￿￿￿￿
!￿￿￿￿￿￿￿￿￿￿!￿￿￿￿￿￿￿￿￿￿￿￿			FWH
￿￿￿￿								PCI Express Slot
			Port 80					￿￿￿￿￿￿￿￿
			PCI 2.2		DB800
CK-409

26Intel® Xeon™ Processor, Intel® E7520 Chipset, Intel® 6300ESB ICH Development Kit User’s Manual