Intel 6300ESB ICH, Xeon PCI PM Support, Platform Management, 2.3.6 S5 State, Wake-Up Events

Platform Management

2.3.6S5 State

This state is the normal off state whether entered through the Power Button or Soft Off. All power is shut off except for the logic required to restart. The system remains in the S5 State only while the power supply is plugged into the electrical outlet. If the power supply is unplugged, this is considered a Mechanical OFF or G3.

2.3.7Wake-Up Events

The types of wake-up events and wake-up latencies are related to the actual power rails available to the system in a particular sleep state, as well as to the location in which the system context is stored. Regardless of the Sleep State, Wake on the Power Button is always supported except in a mechanical off situation. When in a Sleep State, the system complies with the PCI specification by supplying the optional 3.3 V standby voltage to each PCI slot as well as the PME# signal. This enables any compliant PCI card to wake up the system from supported sleep states except Mechanical Off.

Note: Wake on USB, Wake on PS/2, and Wake on LAN are not supported.

2.3.8Wake-Up from S1 Sleep State

During S1, the system is fully powered, permitting support for PCI Express* Wake and Wake on PCI PME#.

2.3.9Wake-Up from S4 and S5 States

The power button is used to wake from S4 and S5.

2.4PCI PM Support

This design holds the system reset signal low when in a sleep state. The system supports the PCI PME# signal and provides 3.3 V standby to the PCI and PCI Express slots. This support allows any compliant PCI or PCI Express card to wake up the system from any sleep state except mechanical off. The user and the operating system must configure the system carefully following the PCI power management interface specification because of the limited amount of power available on

3.3 V standby.

2.5Platform Management

The LM 93 monitors the majority of the system voltages. The VID signals from the processors are also monitored by LM 93. All voltage levels can be read via the SMBus.

Intel® Xeon™ Processor, Intel® E7520 Chipset, Intel® 6300ESB ICH Development Kit User’s Manual 15