Intel Xeon 2.3.2 S1 State, 2.3.3 S2 State, 2.3.4 S3 State, 2.3.5 S4 State, Platform Management

Platform Management

2.3.2S1 State

This state is entered via a processor Sleep signal from the I/O controller (processor C3 state). The system remains fully powered with memory contents intact but the processors enter their lowest power state. The operating system disables bus masters for uniprocessor configurations while flushing and invalidating caches before entering this state in multiprocessor configurations. Wake- up latency is slightly longer in this state than in S0; however, power savings are improved from S0.

2.3.3S2 State

This state is not supported.

2.3.4S3 State

This state is called Suspend to RAM (STR). The system context is maintained in system DRAM, but power is shut off to non-critical circuits. Memory is retained, and refreshes continue. All clocks stop except the RTC. S3 is entered when the I/O controller asserts the SLP_S3# signal to downstream circuitry to control 1.8 V power plane switching. Power must be switched from the normal 1.8 V rail to standby 1.8 V, because the EPS-12V 550 W power supply does not directly supply a standby 1.8 V rail. The sequence to enter Suspend to RAM is as follows:

1.The OS and BIOS prepare for S3 sleep state.

2.The OS sets the appropriate sleep bits in the I/O controller.

3.The I/O controller drives STPCLK to the processors.

4.The processors respond with a Stop-Grant cycle, passed over hub interface by MCH.

5.The I/O controller indicates an S3 (STR) sleep mode to the MCH via Hub Interface A.

6.The MCH puts DDR memory into the self-refresh mode.

7.The MCH drives DDR CMDCLK differential pairs and all DDR outputs low.

8.The MCH drives a completion message via Hub Interface A to the I/O controller.

9.The I/O controller turns off all voltage rails (except Standby 5V) from the main power supply by asserting the SLP_S3_N signal.

—When in the S3 state, only the Standby 5 V rail is available from the power supply. The board uses this standby source to generate 1.8 V standby rail to power the DIMMs.

—The asserted SLP_S3_N signal also controls the logic to switch the DIMM power source from main 1.8 V to standby 1.8 V.

2.3.5S4 State

This state is called Suspend to Disk. From a hardware perspective, it is equivalent to an S5 state. The operating system is responsible for saving the system context in a special partition on the hard drive. Although the system must power up and fully boot, boot time to an application is reduced because the platform is returned to the same system state as when the preceding power off occurred.

14Intel® Xeon™ Processor, Intel® E7520 Chipset, Intel® 6300ESB ICH Development Kit User’s Manual