SEMICONDUCTOR DATA
PLL System : SC370651F or MC145190F-K (PLLIVCO I C I )
Terminal connection diagram
REFin
Din
CLK
VPD |
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| OUTPUT A | |
P ; | I_UTP: : : | i3 | ||
Rx |
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| TEST2 |
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TEST1 | 9 | 12 | Vcc |
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- | 10 | 11 | fin |
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fin |
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Block diagram
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| - | DATA OUT |
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| 20 | P |
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| f R |
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REFln | OSC OR |
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- |
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| SELECTLOGIC | 5OUTPUT A | |||
| 4 STAGE |
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| 1 | DIVIDER | 1 | / |
| N |
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REFout - | (CONFIGURABLE) |
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/ 3 | / 13 |
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DOUBLE BUFFERED
* Bit GrabberTMR REGISTER
16 BlTS
t
Bit Grabberm C REGISTER
'1 8 BITS I
STANDBY POR
LOGIC
Bn Grabberm A REGISTER
+2 4 BlTS
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| A COUNTER | N COUNTER |
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fin 11 |
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- 10 | 64/65 |
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PRESCALER | CONTROL |
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fin | t | LOGIC |
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SUPPLY CONNECTIONS : | I A | Y y TEST1 | |
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PIN12= VCC (VcTO INPUT AMP AND 64/55pnCSCALERl |
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PIN5 = VPD(VcTO PHASEIFREQUENCY | '9RSA AND 8) |
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PIN14= VDD(V+TO BALANCE OF Cl'.f'. |
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PIN7 = GND (COMMON GROUND: