Functional Details |
Control Register BASE + 6h
TRGPOL TRGSEL | TRGCLR | CLK2 | CTR1 |
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| 10K |
| 5 | 39 | CRT1 CLK |
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| 5 | 10K | 40 |
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| CTR1 GATE | ||
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| GATE |
| OUT |
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| Counter 1 |
| 41 | CTR1 OUT | |
| 1/10 |
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| CLK |
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| 1/10 | 0 |
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| CLK |
| OUT |
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| 1 |
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| Counter 2 |
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| GATE |
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| 10 MHz |
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| CLK |
| OUT | 47 | A/D INTERNAL |
| OSC |
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| Counter 3 |
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| PACER OUT | |
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| GATE |
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| Trigger |
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| 44 | A/D PACER GATE |
| Logic |
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| 45 | A/D EXTERNAL |
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| TRIGGER | |
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| TS1 | TS0 | Control register |
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| BASE + 4h |
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| A/D Convert CLock | 1 | 0 | 3 |
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| MUX | 2 | Trigger |
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| A/D EXTERNAL | |||
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| 1 |
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| 42 | ||||
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| Logic |
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| CLOCK | ||
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| 0 |
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| S/W CONVERT |
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Figure 9. Counter/pacer logic diagram
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