Analog output pacing and triggering
| Table 12. Analog output pacing and triggering specifications | |
|
|
|
D/A pacing |
| Internal counter – ASIC |
| External source (D/A external pacer) | |
|
| Software paced |
D/A gate sources |
| External digital (external D/A trigger/pacer gate) |
|
| |
| External analog (analog trigger in) | |
D/A gating modes |
| External digital: Programmable, active high or active low, level or edge |
|
| External analog: |
|
| set by DAC0 or DAC1. |
D/A trigger sources |
| External digital (external D/A trigger/pacer gate) |
|
| Software triggered |
D/A triggering modes |
| External digital: |
Data transfer |
| From 16 k RAM buffer via DMA (demand or |
|
| Programmed I/O |
|
| 100 kS/s max per channel |
Digital input/output
Table 13. Digital I/O specifications
Digital type (main connector) | Output: 74LS175 | |
| Input: 74LS244 | |
Configuration | Four inputs, four outputs (DIN0 through DIN3; DOUT0 to DOUT3) | |
Output high voltage (IOH = | 2.7 | V min |
Output low voltage (IOL = 8 mA) | 0.5 | V max |
Input high voltage | 2.0 | V min, 7 volts absolute max |
Input low voltage | 0.8 | V max, |
Digital type (digital I/O connector) | 82C55 | |
Number of I/O | 24 (FIRSTPORTA Bit 0 through FIRSTPORTC Bit 7) | |
Configuration | 2 banks of 8 and 2 banks of 4, or | |
| 3 banks of 8 or | |
| 2 banks of 8 with handshake | |
Input high voltage | 2.0 | V min, 5.5 V absolute max |
Input low voltage | 0.8 | V max, |
Output high voltage (IOH = | 3.0 | V min |
Output low voltage (IOL = 2.5 mA) | 0.4 | V max |
Input mode (high impedance) | ||
SSH output | TTL compatible output, HOLD is asserted from start of the conversion for | |
| Channel 0 through conversion of the last channel in the scan. Available at user | |
| connector (SSH OUT / D/A PACER OUT). This pin is software selectable as | |
| SSH OUT (default) or D/A PACER OUT. | |
SSH polarity | HOLD high (default) or HOLD low, software selectable | |
