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| The BIOS also issues Port 80h codes that can be displayed using a suitable diagnostic card. The | ||||||
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| 02h |
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| Verify Real Mode |
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| 03h |
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| Disable |
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| 04h |
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| Get CPU type |
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| 06h |
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| Initialise system hardware |
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| 08h |
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| Initialise chipset with initial POST values |
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| 09h |
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| Set IN POST flag |
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| 0Ah |
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| Initialise CPU registers |
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| 0Bh |
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| Enable CPU cache |
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| 0Ch |
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| Initialise caches to initial POST values |
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| 0Eh |
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| Initialise I/ O component |
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| 0Fh |
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| Initialise the local bus IDE |
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| 10h |
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| Initialise Power Management |
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| 11h |
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| Load alternate registers with initial POST values |
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| 12h |
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| Restore CPU control word during warm boot |
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| 13h |
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| Initialise PCI Bus Mastering devices |
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| 14h |
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| Initialise keyboard controller |
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| 16h |
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| BIOS ROM checksum |
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| 17h |
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| Initialise cache before memory autosize |
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| 18h |
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| 8254 timer initialisation |
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| 1Ah |
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| 8237 DMA controller initialisation |
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| 1Ch |
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| Reset Programmable Interrupt Controller |
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| 20h |
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| Test DRAM refresh |
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| 22h |
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| Test 8742 Keyboard Controller |
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| 24h |
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| Set ES segment register to 4 GB |
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| 26h |
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| Enable A20 line |
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| 28h |
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| Autosize DRAM |
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| 29h |
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| Initialise POST Memory Manager |
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| 2Ah |
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| Clear 512 KB base RAM |
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| 2Ch |
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| RAM failure on address line |
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| 2Eh |
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| RAM failure on data bits of low byte of memory bus |
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| 2Fh |
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| Enable cache before system BIOS shadow |
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| 30h |
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| RAM failure on data bits of high byte of memory bus |
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| 32h |
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| Test CPU bus- clock frequency |
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| 33h |
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| Initialise Phoenix Dispatch Manager |
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| 34h |
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| Test CMOS RAM |
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| 35h |
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| Initialise alternate chipset registers. |
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MITSUBISHI ELECTRIC MOTHERBOARD DIVISION | PAGE 30 OF 45 |
